p87c51mc2 NXP Semiconductors, p87c51mc2 Datasheet - Page 8

• Manufacturer Part Number: p87c51mc2
• Description: 80c51 8-bit Microcontroller Family With Extended Memory
• Manufacturer: NXP Semiconductors

2001 Apr 06
Philips Semiconductors
MNEMONIC
P4.0 - P4.1
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
(NC/V
(NC/V
EA/Vpp
XTAL1
XTAL2
PSEN
RST
ALE
V
V
DD
SS
DD
SS
)
)
PIN NO.
12,34
12
34
10
33
32
35
21
20
22
44
23
1
TYPE NAME AND FUNCTION
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups on all pin. Port 4 pins
that have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 4 pins that are externally pulled low will source current because of
the internal pull-ups. (Note: When SFR bit SPEN (SPCTL.6) is ’1’, the pull-ups at these port
pins are disabled.)
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V
capacitor to V
Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory. If SFR bit AO (AUXR.0) is
’0’, ALE is emitted at the constant rate as indicated above. With this bit set to ’1’, ALE will
be active only during a MOVX instruction.
Program Store Enable: The read strobe to external program memory. When executing
code from the external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
External Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations. If EA is held
high, the device executes from internal program memory. The value on the EA pin is
latched when RST is released and any subsequent changes have no effect.
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
Crystal 2: Output from the inverting oscillator amplifier.
Ground: 0V reference.
Power Supply: This is the power supply voltage for normal operation as well as Idle and
Power Down modes.
No Connect/Ground: This pin is a no connect pin on some derivatives, but is internally
connected to V
connected to the same V
pins is not required. However, they may be connected in addition to the primary V
V
system-level EMI characteristics.)
No Connect/Power Supply: This pin is a no connect pin on some derivatives, but is
internally connected to V
be connected to the same V
V
and V
system-level EMI characteristics.)
DD
DD
P4.0
P4.1
pins to improve power distribution, reduce noise in output signals, and improve
pins is not required. However, they may be connected in addition to the primary V
DD
pins to improve power distribution, reduce noise in output signals, and improve
RXD1
MISO
TXD1
SS
DD.
SS
on the P87C51Mx2. If connected externally, this pin must only be
Serial input port 1. (Note: This pin is a no connect pin on some
derivatives.) (with pull-up on pin)
SPI Master In/Slave Out (Selected when SFR bit SPEN (SPCTL.6)
is ’1’, in which case the pull-up for this pin is disabled)
Serial output port 1. (Note: This pin is a no connect pin on some
derivatives.) (with pull-up on pin)
SPI Slave Select (Selected when SFR bit SPEN (SPCTL.6) is ’1’,
in which case the pull-up for this pin is disabled)
SS
DD
8
as at pin 22. (Note: Connecting the second pair of V
on the P87C51Mx2. If connected externally, this pin must only
DD
as at pin 44. (Note: Connecting the second pair of V
SS
permits a power-on reset using only an external
P87C51MB2/P87C51MC2
Preliminary specification
SS
SS
and V
SS
and
and
SS
DD