p89c538nbb NXP Semiconductors, p89c538nbb Datasheet - Page 13

• Manufacturer Part Number: p89c538nbb
• Description: Cmos Single-chip 8-bit Microcontrollers With Flash Program Memory
• Manufacturer: NXP Semiconductors

1. L = Level activated
2. T = Transition activated
Philips Semiconductors
Interrupt Priority Structure
The 89C536/538 has a 6-source two-level interrupt structure (see
Table 7). There are 2 SFRs associated with the interrupts on the
89C536/538. They are the IE and IP. (See Figures 6 and 7.)
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
Table 7.
NOTES:
1998 Apr 24
PRIORITY BITS
80C51 8-bit microcontroller family
16K/64K/512 FLASH
IP.x
0
1
SOURCE
BIT
IE.7
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
SP
X0
T0
X1
T1
T2
Interrupt Table
IE (0A8H)
IP (0B8H)
Level 0 (lowest priority)
Level 1 (highest priority)
SYMBOL
EA
—
ET2
ES
ET1
EX1
ET0
EX0
SYMBOL
—
—
PT2
PS
PT1
PX1
PT0
PX0
INTERRUPT PRIORITY LEVEL
INTERRUPT PRIORITY LEVEL
POLLING PRIORITY
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
FUNCTION
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
Not implemented.
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
FUNCTION
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit.
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
External interrupt 1 priority bit.
Timer 0 interrupt priority bit.
External interrupt 0 priority bit.
EA
—
7
7
1
2
3
4
5
6
—
—
6
6
ET2
PT2
5
5
Figure 6.
Figure 7.
REQUEST BITS
ES
PS
4
4
TF2, EXF2
R1, TI
TP0
TF1
IE0
IE1
13
IE Registers
IP Registers
ET1
PT1
3
3
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
EX1
PX1
2
2
HARDWARE CLEAR?
N (L)
ET0
PT0
N (L) Y (T)
1
1
1
Y
Y
N
N
Y (T)
SU00572
EX0
PX0
0
0
2
89C536/89C538
VECTOR ADDRESS
Preliminary specification
SU00571
0BH
1BH
2BH
03H
13H
23H