p89c538nbb NXP Semiconductors, p89c538nbb Datasheet - Page 14

• Manufacturer Part Number: p89c538nbb
• Description: Cmos Single-chip 8-bit Microcontrollers With Flash Program Memory
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Expanded Data RAM Addressing
The 89C536/538 has internal data memory that is mapped into four
separate segments: the lower 128 bytes of RAM, upper 128 bytes of
RAM, 128 bytes Special Function Register (SFR), and 256 bytes
expanded RAM (ERAM).
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are
2. The Upper 128 bytes of RAM (addresses 80H to FFH) are
3. The Special Function Registers, SFRs, (addresses 80H to FFH)
4. The 256-bytes expanded RAM (ERAM, 00H – FFH) are indirectly
The Lower 128 bytes can be accessed by either direct or indirect
addressing. The Upper 128 bytes can be accessed by indirect
addressing only. The Upper 128 bytes occupy the same address
space as the SFRs. That means they have the same address, but
are physically separate from SFR space.
When an instruction accesses an internal location above address
7FH, the CPU knows whether the access is to the upper 128 bytes
of data RAM or to SFR space by the addressing mode used in the
instruction. Instructions that use direct addressing access SFR
space. For example:
accesses the SFR at location 0A0H (which is P2). Instructions that
use indirect addressing access the Upper 128 bytes of data RAM.
1998 Apr 24
80C51 8-bit microcontroller family
16K/64K/512 FLASH
MOV 0A0H,#data
directly and indirectly addressable.
indirectly addressable only.
are directly addressable only.
accessed by move external instruction, MOVX.
FF
00
256 BYTES
ERAM
Figure 8.
FF
80
00
Internal and External Data Memory Address Space
INTERNAL RAM
INTERNAL RAM
128 BYTES
128 BYTES
LOWER
UPPER
14
FF
80
00
For example:
where R0 contains 0A0H, accesses the data byte at address 0A0H,
rather than P2 (whose address is 0A0H).
The ERAM can be accessed by indirect addressing and MOVX
instructions. This part of memory is physically located on-chip,
logically occupies the first 256-bytes of external data memory.
The ERAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or
DPTR. An access to ERAM will not affect ports P0, P3.6 (WR#) and
P3.7 (RD#). P2 SFR is output during external addressing.
For example,
where R0 contains 0A0H, accesses the ERAM at address 0A0H
rather than external memory. An access to external data memory
locations higher than FFH (i.e., 0100H to FFFFH) will be performed
with the MOVX DPTR instructions in the same way as in the
standard 80C51, so with P0 and P2 as data/address bus, and P3.6
and P3.7 as write and read timing signals. Refer to Figure 8.
External data memory cannot be accessed using the MOVX with R0
or R1. This will always access the ERAM.
The stack pointer (SP) may be located anywhere in the 256 bytes
RAM (lower and upper RAM) internal data memory. The stack may
not be located in the ERAM.
MOV @R0,#data
MOVX @R0,#data
FUNCTION
REGISTER
SPECIAL
FFFF
0100
0000
EXTERNAL
MEMORY
DATA
89C536/89C538
Preliminary specification
SU00868