mc9s08sh8mwjr Freescale Semiconductor, Inc, mc9s08sh8mwjr Datasheet - Page 60

• Manufacturer Part Number: mc9s08sh8mwjr
• Description: S08sh 5-volt 8-bit Microcontrollers With Sci, Spi, I2c, Adc And Analog Comparators
• Manufacturer: Freescale Semiconductor, Inc

Chapter 5 Resets, Interrupts, and General System Control
5.4
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter
before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COP watchdog is enabled (see
for additional information). If the COP watchdog is not used in an application, it can be disabled by
clearing COPT bits in SOPT1.
The COP counter is reset by writing 0x0055 and 0x00AA (in this order) to the address of SRS during the
selected timeout period. Writes do not affect the data in the read-only SRS. As soon as the write sequence
is done, the COP timeout period is restarted. If the program fails to do this during the time-out period, the
MCU will reset. Also, if any value other than 0x0055 or 0x00AA is written to SRS, the MCU is
immediately reset.
The COPCLKS bit in SOPT2 (see
information) selects the clock source used for the COP timer. The clock source options are either the bus
clock or an internal 1-kHz clock source. With each clock source, there are three associated time-outs
controlled by the COPT bits in SOPT1.
COPT bits. The COP watchdog defaults to operation from the 1-kHz clock source and the longest time-out
(2
When the bus clock source is selected, windowed COP operation is available by setting COPW in the
SOPT2 register. In this mode, writes to the SRS register to clear the COP timer must occur in the last 25%
of the selected timeout period. A premature write immediately resets the MCU. When the 1-kHz clock
source is selected, windowed COP operation is not available.
60
1
2
10
Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column
displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode
(COPW = 1).
Values shown in milliseconds based on t
tolerance of this value.
COPCLKS
cycles).
N/A
0
0
0
1
1
1
Computer Operating Properly (COP) Watchdog
Control Bits
COPT[1:0]
0:0
0:1
1:0
1:1
0:1
1:0
1:1
Table 5-1. COP Configuration Options
Clock Source
Section 5.7.5, “System Options Register 2
MC9S08SH32 Series Data Sheet, Rev. 2
LPO
1 kHz
1 kHz
1 kHz
Bus
Bus
Bus
N/A
= 1 ms. See t
Table 5-1
PRELIMINARY
summaries the control functions of the COPCLKS and
COP Window
LPO
Section 5.7.4, “System Options Register 1
196,608 cycles
49,152 cycles
in the appendix
(COPW = 1)
6144 cycles
N/A
N/A
N/A
N/A
1
Opens
Section A.12.1, “Control
(SOPT2),” for additional
COP Overflow Count
2
2
2
10
8
5
COP is disabled
cycles (256 ms
cycles (32 ms
cycles (1.024 s
2
2
2
Freescale Semiconductor
13
16
18
cycles
cycles
cycles
Timing,” for the
(SOPT1),”
2
1
1
)
)
)