mc9s08sh8mwjr Freescale Semiconductor, Inc, mc9s08sh8mwjr Datasheet - Page 62

• Manufacturer Part Number: mc9s08sh8mwjr
• Description: S08sh 5-volt 8-bit Microcontrollers With Sci, Spi, I2c, Adc And Analog Comparators
• Manufacturer: Freescale Semiconductor, Inc

Chapter 5 Resets, Interrupts, and General System Control
other than the most experienced programmers because it can lead to subtle program errors that are difficult
to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR,
A, X, and PC registers to their pre-interrupt values by reading the previously saved information from the
stack.
If more than one interrupt is pending when the I bit is cleared, the highest priority source is serviced first
(see
5.5.1
Figure 5-1
(SP) points at the next available byte location on the stack. The current values of CPU registers are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack which is the address that is one less than
the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of
the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address recovered from the stack.
62
Table
5-2).
shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
Interrupt Stack Frame
For compatibility with M68HC08 devices, the H register is not
automatically saved and restored. It is good programming practice to push
H onto the stack at the start of the interrupt service routine (ISR) and restore
it immediately before the RTI that is used to return from the ISR.
STACKING
ORDER
UNSTACKING
5
4
3
2
1
ORDER
1
2
3
4
5
MC9S08SH32 Series Data Sheet, Rev. 2
Figure 5-1. Interrupt Stack Frame
* High byte (H) of index register is not automatically stacked.
7
INDEX REGISTER (LOW BYTE X)
CONDITION CODE REGISTER
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
PRELIMINARY
ACCUMULATOR
NOTE
TOWARD HIGHER ADDRESSES
TOWARD LOWER ADDRESSES
*
0
SP AFTER
INTERRUPT STACKING
SP BEFORE
THE INTERRUPT
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