xrt83l30 Exar Corporation, xrt83l30 Datasheet
xrt83l30
Available stocks
Related parts for xrt83l30
xrt83l30 Summary of contents
Page 1
... Both B8ZS and HDB3 encoding and decoding functions are included and can be disabled as required. On-chip crystal-less jitter attenuator with bit FIFO can be placed either in the receive or the transmit path with loop bandwidths of less than 3Hz. The XRT83L30 IGURE ...
Page 2
... Crystal-less digital jitter attenuator with 32-bit or 64-bit FIFO Selectable either in transmit or receive path • On-chip frequency multiplier generates Master clocks from variety of external clock sources • On-chip transmit short-circuit protection and limiting, and driver fail monitor output (DMO) XRT83L30 T1/E1/J1 LIU (H ARDWARE TAOS ENABLE TX/RX JITTER ...
Page 3
... Logic inputs accept either 3. levels • Single +3.3V Supply Operation • 64 pin TQFP package • -40°C to +85°C Temperature Range P N ART UMBER XRT83L30IV ORDERING INFORMATION P ACKAGE 64 Lead TQFP ( 1.4mm) 3 XRT83L30 PERATING EMPERATURE ANGE ° ° - +85 C ...
Page 4
... TXTEST0 57 TCLKE 58 TXON 59 ICT 60 TCLK 61 TPOS / TDATA 62 TNEG / CODES 63 RLOS 64 RCLK XRT83L30 REV. 1.0.1 AGND AVDD LOOP0 LOOP1 ATAOS TRATIO EQC0 / INT EQC1 / CS EQC2 / SCLK EQC3 / SDO EQC4 / SDI HW/HOST CLKSEL0 CLKSEL1 CLKSEL2 ...
Page 5
... SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR GENERAL DESCRIPTION .................................................................................................. 1 A .............................................................................................................................................. 1 PPLICATIONS F ................................................................................................................................................... 1 EATURES Figure 1. Block Diagram of the XRT83L30 T1/E1/J1 LIU (Host Mode) ................................................. 1 Figure 2. Block Diagram of the XRT83L30 T1/E1/J1 LIU (Hardware Mode) ........................................ 2 F ................................................................................................................................................... 2 EATURES ORDERING INFORMATION ............................................................................................................... 3 Figure 3. Pin Out of the XRT83L30 ......................................................................................................... 4 TABLE OF CONTENTS ....................................................................................................... I PIN DESCRIPTIONS BY FUNCTION ...
Page 6
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR RECEIVER ............................................................................................................................................... 27 Internal Receive Termination Mode .................................................................................................................. ABLE ECEIVE ERMINATION Figure 13. Simplified Diagram for the Internal Receive and Transmit Termination Mode ............... ABLE ECEIVE ERMINATIONS Figure 14. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) .................... 28 Figure 15 ...
Page 7
... ICROPROCESSOR T 36 ABLE ICROPROCESSOR E C .................................................................................................................. 65 LECTRICAL HARACTERISTICS T 37 ABLE BSOLUTE AXIMUM T 38 ABLE IGITAL NPUT AND T 39: XRT83L30 P C ABLE OWER T 40 ABLE ECEIVER LECTRICAL T 41 ABLE ECEIVER LECTRICAL T 42 ABLE RANSMIT ETURN T 43 ...
Page 8
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PIN DESCRIPTIONS BY FUNCTION SERIAL INTERFACE IGNAL AME IN YPE HW/HOST 20 SDI 21 EQC4 SDO 22 O EQC3 SCLK 23 EQC2 CS 24 EQC1 INT 25 O EQC0 D I Mode Control Input This pin is used for selecting Hardware or Host mode to control the device. ...
Page 9
... In Hardware mode, with this pin set to ‘High’ the output receive data is updated on the falling edge of RCLK. With this pin tied ‘Low’, output data is updated on the rising edge of RCLK Internally pulled “Low” with a 50kΩ resistor. OTE 6 XRT83L30 ESCRIPTION ...
Page 10
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TRANSMITTER IGNAL AME IN YPE TTIP 8 O TRING 10 O TPOS 61 TDATA TNEG 62 CODES TCLK 60 TCLKE 57 TXON 58 D Transmitter Tip Output Positive differential transmit output to the line. Transmitter Ring Output Negative differential transmit output to the line. ...
Page 11
... TLUC (Transmit Network Loop-Up Code): Activating this condition enables the Network Loop-Up Code of "00001" transmitted to the line. When Network Loop-Up code is being transmitted, the XRT83L30 will ignore the Automatic Loop-Code detection and Remote Loop-back activation (NLCDE1=”1”, NLCDE0=”1”, if activated) in order to avoid activating Remote Digital Loop-back automatically when the remote terminal responds to the Loop-back request ...
Page 12
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR JITTER ATTENUATOR IGNAL AME IN YPE JABW 46 JASEL1 47 JASEL0 48 CLOCK SYNTHESIZER IGNAL AME IN YPE MCLKE1 Jitter Attenuator Bandwidth In Hardware and E1 mode, when JABW=”0” the jitter attenuator bandwidth is 10Hz (normal mode). Setting JABW to “ ...
Page 13
... 128 X 1 128 X 1 256 X 1 256 Internally pulled "Low" with a 50kΩ resistor. OTE 10 XRT83L30 ESCRIPTION CLKOUT CLKSEL1 CLKSEL0 MCLKRATE (KHz 2048 1544 2048 1544 2048 ...
Page 14
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REDUNDANCY SUPPORT IGNAL AME IN YPE DMO 11 O TERMINATIONS IGNAL AME IN YPE GAUGE 49 TRATIO 26 RXTSEL 44 TXTSEL 45 D Driver Failure Monitor This pin transitions "High" short circuit condition is detected in the trans- mit driver transmit output pulse is detected for more than 128 TCLK cycles ...
Page 15
... RXTSEL “High”. RXRES1 RXRES0 Internally pulled “Low” with 50kΩ resistor. OTE 12 XRT83L30 ESCRIPTION Termination 0 100Ω Ω 1 110 75 Ω 120Ω RX Fixed Resistor No External Fixed Resistor 240Ω ...
Page 16
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR CONTROL FUNCTION RESET 41 SR/DR 28 LOOP1 29 LOOP0 30 EQC4 21 SDI EQC3 22 SDO O EQC2 23 SCLK I Hardware Reset (Active "Low") When this pin is tied “Low” for more than 10µs, the device is put in the reset state. ...
Page 17
... When this pin is tied “Low”, all output pins are forced to a “High” impedance state for in-circuit testing. Pulling RESET “Low” while ICT pin is also “Low” will put the chip in factory test mode. This condition should never happen during normal operation Internally pulled “High” with a 50kΩ resistor. OTE 14 XRT83L30 ESCRIPTION ...
Page 18
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR ALARM FUNCTION/OTHER IGNAL AME IN YPE NLCDE1 33 NLCDE0 34 INSBPV Network Loop Code Detection Enable pin 1 Network Loop Code Detection Enable pin 0 NLCDE[1:0] pins are used to control the Loop-Code detection according to ...
Page 19
... Transmitter Analog Positive Supply (3.3V + 5%) Receiver Analog Ground Receiver Analog Positive Supply (3.3V± 5%) Analog Positive Supply for Master Clock Synthesizer PLL (3.3V± 5%) Analog Ground for Master Clock Synthesizer PLL Digital Positive Supply (3.3V± 5%) Analog Positive Supply (3.3V± 5%) Digital Ground Analog Ground 16 XRT83L30 ...
Page 20
... The XRT83L30 is a fully integrated single channel long-haul and short-haul transceiver intended for T1 systems. Simplified block diagrams of the device are shown in Hardware mode. The XRT83L30 can receive signals that have been attenuated from 0 to 36dB at 772kHz (0 to 6000 feet cable loss) for T1 and from 0 to 43dB at 1024kHz for E1 systems. ...
Page 21
... SEE”MICROPROCESSOR REGISTER #2 BIT 18 XRT83L30 M C ASTER LOCK MCLKRATE 2048 1 1544 0 2048 1 1544 0 2048 1 1544 0 2048 1 1544 0 2048 1 1544 0 2048 1 1544 0 2048 1 ...
Page 22
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR RECEIVE MONITOR MODE In applications where Monitor mode is desired, the equalizer can be configured in a gain mode which handles input signals attenuated resistively up to 29dB, along with 0 to 6dB cable attenuation for both T1 and E1 ...
Page 23
... Norm alized up to +29dB Max Figure 8 for a simplified diagram RLOS C ONG AUL ODE AND Norm alized up to +36dB Max -9dB Clear LOS +3dB Declare LOS Declare LOS Clear LOS Norm alized up to +36dB Max 20 XRT83L30 Figure 7 for a simplified diagram. ONDITION ONDITION ...
Page 24
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR cable loss (frequency), not flat loss (resistive). Once the E1 input signal has been normalized to 0dB by adding the maximum gain (+43dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is typically -52dB (-43dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to clear ...
Page 25
... GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) The XRT83L30 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple timing domains. As the higher data rates are de-multiplexed down data, stuffing bits are removed which can leave gaps in the incoming data stream ...
Page 26
... TRANSMIT CLOCK (TCLK) SAMPLING EDGE Serial transmit data at TPOS/TDATA and TNEG/CODE are clocked into the XRT83L30 under the synchronization of TCLK. With a “0” written to the TCLKE interface bit pulling the TCLKE pin “Low”, input data is sampled on the falling edge of TCLK. The sampling edge is inverted with a “ ...
Page 27
... B8ZS E ABLE XAMPLES OF NCODING ASE RECEDING ULSE Input + 00000000 000VB0VB + 000+ - ASE Input - 00000000 000VB0VB - 000- + XRT83L30 TCLK TCLK R F Table system, an Table N 4 EXT BITS 0000 000V B00V 8 B EXT ITS 4. ...
Page 28
... Table 5. For CSU LBO transmit pulse design information, refer to ANSI T1.403-1993 Network-to-Customer Installation specification, Annex- EQC[4:0] determine the T1/E1 operating mode of the XRT83L30. When EQC4 = “1” and EQC3 = “1”, the XRT83L30 OTE is in the E1 mode, otherwise the T1/J1 mode. T ...
Page 29
... E1 Long Haul/43dB ITU G.703 0 E1 Short Haul ITU G.703 1 E1 Short Haul ITU G.703 0 E1 Gain Mode ITU G.703 1 E1 Gain Mode ITU G.703 26 XRT83L30 UILD UT ETTINGS LBO C C ABLE ODING 100Ω/ TP B8ZS 100Ω/ TP B8ZS 100Ω/ TP B8ZS 100Ω ...
Page 30
... SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TRANSMIT AND RECEIVE TERMINATIONS The XRT83L30 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide applications for T1, J1 and E1. For specific applications the internal terminations can be disabled to allow the use of existing components and/or designs ...
Page 31
... Figure simplified diagram for T1 (100Ω) in the external receive termination mode. simplified diagram for E1 (75Ω) in the external receive termination mode. F 14. S IGURE IMPLIFIED XRT83L30 LIU ABLE ECEIVE ERMINATIONS RXRES1 RXRES0 ...
Page 32
... RANSMIT ERMINATION By default the XRT83L30 is set for external termination mode at power Hardware reset. When external transmit termination mode is selected, the internal termination circuitry is disabled. The value of the external resistors is chosen for a specific application according to the turns ratio selected by TRATIO (Pin 26) in Hardware mode or bit 0 in the appropriate register in Host mode, see “ ...
Page 33
... System designers can achieve this by implementing common redundancy schemes with the XRT83L30 Line Interface Unit (LIU). The XRT83L30 offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. These features allow system designers to implement redundancy applications that ensure reliability ...
Page 34
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PROGRAMMING CONSIDERATIONS In many applications switching the control of the transmitter outputs and the receiver line impedance to hardware control will provide faster transmitter ON/OFF switching. In Host Mode, there are two bits in register 18 (12H) that control the transmitter outputs and the Rx line impedance select, TXONCNTL (Bit 5) and TERCNTL (Bit 4). Setting bit-5 (TXONCNTL “ ...
Page 35
... Backup Card RxTSEL=0, External N+1 REDUNDANCY IAGRAM OF THE RANSMIT ECTION FOR Line Interface Card XRT83L30 0.68µF Tx XRT83L30 0.68µ LOCK IAGRAM ECEIVE ECTION FOR Line Interface Card XRT83L30 Rx XRT83L30 Rx 32 XRT83L30 1:1 & 1+1 R EDUNDANCY 1:2 T1/E1 Line Figure 17 for a 1:1 1+1 R AND EDUNDANCY 1:1 T1/E1 Line ...
Page 36
... This allows all transmitters and receivers on the primary cards to be configured in internal impedance mode, providing one bill of materials for all interface modes of operation. The transmit and receive sections of the XRT83L30 are described separately. TRANSMIT For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance mode providing one bill of materials for T1/E1/J1 ...
Page 37
... LOCK IAGRAM Backplane Interface Primary Card RxTSEL=1, Internal Primary Card RxTSEL=1, Internal Primary Card RxTSEL=1, Internal Backup Card RxTSEL=1, External - R S N+1 R ECEIVE ECTION FOR EDUNDANCY Line Interface Card XRT83L30 Rx XRT83L30 Rx XRT83L30 Rx XRT83L30 Rx 34 XRT83L30 Figure 19. for a simplified block 1:1 T1/E1 Line 1:1 T1/E1 Line 1:1 T1/E1 Line ...
Page 38
... Loop-back and the chip is receiving its own transmitted data. When Network Loop-Up code is being transmitted the XRT83L30 will ignore the Auto- matic Loop-Code detection and Remote Loop-back activation (NLCDE1=”1”, NLCDE0=”1”, if activated) in order to avoid activating Remote Digital Loop-back automatically when the remote terminal responds to the Loop-back request ...
Page 39
... NLCD bit changes provided the Network Loop-code interrupt is enabled. TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) The XRT83L30 includes a QRSS pattern generation and detection block for diagnostic purposes that can be activated only in the Host mode by setting the interface bits TXTEST2=”1”, TXTEST1=”0” and TXTEST0=”0”. ...
Page 40
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR With TDQRSS activated, a bit error can be inserted in the transmitted QRSS pattern by transitioning the INSBER interface bit from “0” to “1”. Bipolar violation can also be inserted either in the QRSS pattern, or input data when operating in the single-rail mode by transitioning the INSBPV interface bit from “0” to “1”. The state of INSBER and INSBPV bits are sampled on the rising edge of the TCLK. To insure the insertion of the bit error or bipolar violation, a “ ...
Page 41
... External inputs at RTIP/RRING in this mode are ignored while valid transmit data continues to be sent to the line. Local Analog Loop-Back exercises most of the functional blocks of the XRT83L30 including the jitter attenuator which can be selected in either the transmit or receive paths. Local Analog Loop-Back is shown in ...
Page 42
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REMOTE LOOP-BACK (RLOOP) With Remote Loop-Back activated, receive data after the jitter attenuator (if selected in the receive path) is looped back to the transmit path using RCLK as transmit timing. In this mode transmit clock and data are ignored, while RCLK and receive data will continue to be available at their respective output pins ...
Page 43
... Encoder TNEG TCLK RCLK RPOS Decoder RNEG L - OOP BACK MODE WITH JITTER ATTENUATOR SELECTED IN Timing JA Control Data & Clock Recovery D - UAL LOOP BACK MODE Timing Tx Control JA Data & Clock Recovery 40 XRT83L30 T RANSMIT PATH TTIP Tx TRING RTIP Rx RRING TTIP TRING RTIP Rx RRING ...
Page 44
... SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR HOST MODE SERIAL INTERFACE OPERATION XRT83L30 has a simple four wire Serial Interface that is compatible with many of the microcontrollers available in the market. The Host mode operation is enabled by connecting pin 20 (HW/HOST “Low”. The Serial Interface provides a total of 32 “ ...
Page 45
... The next five rising edges of the SCLK signal, clock in the 5-bit address value for the Read or Write operation. These five bits define the register address within XRT83L30 that the user has selected to read data from or write data to. The address bits must be supplied to the SDI input in ascending order with LSB (Least Significant Bit) first ...
Page 46
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T ABLE R EGISTER R N EGISTER UMBER HEX 0x00 - 0x12 0x13 - 0x15 0x16 - 0x1D 30 0x1E 31 0x1F T ABLE DDRESS IT T YPE Control Registers 0 00000 R/W Reserved Hex 0x00 1 00001 R/W RXTSEL ...
Page 47
... B4S8 ATAOS RCLKE TCLKE CLKSEL2 CLKSEL1 CLKSEL0 GAUGE0 TXONCNTL TERCNTL Reset = 0 Reset = 0 Reset = 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved F9 44 XRT83L30 B3S8 B2S8 B1S8 B0S8 DATAP Reserved Reserved SRESET MCLKRATE RXMUTE ...
Page 48
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 18: M ABLE R A EGISTER DDRESS 00000 AME D7 Reserved D6 Reserved D5 Reserved D4 EQC4 Equalizer Control bit 4: This bit together with EQC[3:0] are used for controlling transmit pulse shaping, transmit line build-out (LBO), receive monitoring and also mode of operation. ...
Page 49
... See description of bit D5 for the function of this bit ICROPROCESSOR EGISTER BIT DESCRIPTION F UNCTION RXTSEL RX Termination 0 External 1 Internal TXTSEL TX Termination 0 External 1 Internal TERSEL1 TERSEL0 Termination 0 0 100Ω 110Ω 75Ω 120Ω 46 XRT83L30 R R EGISTER ESET T V YPE ALUE R/W 0 R/W 0 R/W 0 R/W 0 ...
Page 50
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 19: M ABLE D3 JASEL1 Jitter Attenuator select bit 1: The JASEL1 and JASEL0 bits are used to disable or place the jitter attenuator in the transmit or receive path. D2 JASEL0 Jitter Attenuator select bit 0: See description of bit D3 for the function of this bit ...
Page 51
... Network Loop-Up Code of "00001" trans- mitted to the line. When Network Loop-Up code is being transmitted, the XRT83L30 will ignore the Automatic Loop-Code detection and Remote Loop-Back activation (NLCDE1 =“1”, NLCDE0 =“1”, if activated) in order to avoid activating Remote Digital Loop-Back automatically when the remote terminal responds to the Loop-Back request ...
Page 52
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 20: M ABLE D3 TXON Transmitter ON: Writing a "1" into this bit location turns on the Transmit Section. A ‘0’ in this bit location, shuts off the transmit- ter. In this mode the TTIP and TRING driver outputs will be tri- stated for power reduction or redundancy applications ...
Page 53
... R #3 ICROPROCESSOR EGISTER BIT DESCRIPTION F UNCTION NLCDE1 NLCDE0 Function Disable Loop-Code 0 0 Detection Detect Loop-Up Code Receive Data Detect Loop-Down Code Receive Data Automatic Loop-Code 1 1 Detection 50 XRT83L30 R R EGISTER ESET T V YPE ALUE R/W 0 R/W 0 R/W 0 R/W 0 ...
Page 54
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 21: M ABLE D4 RXRES1 Receive External Resistor Control pin 1: In Host mode, this bit along with the RXRES0 bit selects the value of the external Receive fixed resistor according to the following table: D3 RXRES0 Receive External Resistor Control bit 0: For function of this bit see description of D4 the RXRES1 bit ...
Page 55
... Loss of Receive Signal interrupt generation, writing a "0" masks it. D0 QRPDIE QRSS Pattern Detection Interrupt Enable: Writing a "1" to this bit enables QRSS pattern detection interrupt generation, writing a "0" masks it ICROPROCESSOR EGISTER BIT DESCRIPTION F UNCTION 52 XRT83L30 R R EGISTER ESET T V YPE ALUE R/W 0 R/W 0 R/W 0 ...
Page 56
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 23: M ABLE R A EGISTER DDRESS 00101 AME D7 Reserved D6 DMO Driver Monitor Output: This bit is set to a "1" to indicate trans- mit driver failure is detected. The value of this bit is based on the current status of DMO. If the DMOIE bit is enabled, any transition on this bit will generate an Interrupt ...
Page 57
... QRSS pat- tern. The value of this bit is based on the current status of Quasi- random pattern detector of. If the QRPDIE bit is enabled, any transition on this bit will generate an Interrupt ICROPROCESSOR EGISTER BIT DESCRIPTION 54 XRT83L30 ...
Page 58
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 24: M ABLE R A EGISTER DDRESS 00110 AME D7 Reserved D6 DMOIS Driver Monitor Output Interrupt Status: This bit is set to a "1" every time when DMO status has changed since last read. D5 FLSIS FIFO Limit Interrupt Status: This bit is set to a " ...
Page 59
... B6S1 -B0S1 is in signed magni- tude format with B6S1 as the sign bit and B0S1 as the least sig- nificant bit (LSB ICROPROCESSOR EGISTER BIT DESCRIPTION F UNCTION R #8 ICROPROCESSOR EGISTER BIT DESCRIPTION F UNCTION 56 XRT83L30 R R EGISTER ESET T V YPE ALUE ...
Page 60
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 27: M ABLE R A EGISTER DDRESS 01001 AME D7 Reserved D6-D0 B6S2 - B0S2 Arbitrary Transmit Pulse Shape, Segment 2 The shape of the transmitted pulse can be made user program- mable by selecting "Arbitrary Pulse" mode, see arbitrary pulse is divided into eight time segments whose com- bined duration is equal to one period of MCLK ...
Page 61
... B6S5 -B0S5 is in signed magni- tude format with B6S5 as the sign bit and B0S5 as the least sig- nificant bit (LSB). R #11 ICROPROCESSOR EGISTER BIT DESCRIPTION F UNCTION R #12 ICROPROCESSOR EGISTER BIT DESCRIPTION F UNCTION 58 XRT83L30 R R EGISTER ESET T V YPE ALUE R/W 0 R/W 0 Table 5 . The R R EGISTER ...
Page 62
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 31: M ABLE R A EGISTER DDRESS 01101 AME D7 Reserved D6-D0 B6S6 - B0S6 Arbitrary Transmit Pulse Shape, Segment 6 The shape of the transmitted pulse can be made user program- mable by selecting "Arbitrary Pulse" mode, see arbitrary pulse is divided into eight time segments whose com- bined duration is equal to one period of MCLK ...
Page 63
... This 7 bit number represents the amplitude of the arbitrary pulse during the eighth time segment. B6S8 -B0S8 is in signed magni- tude format with B6S8 as the sign bit and B0S8 as the least sig- nificant bit (LSB). R #15 ICROPROCESSOR EGISTER BIT DESCRIPTION F UNCTION 60 XRT83L30 R R EGISTER ESET T V YPE ALUE R/W 0 R/W ...
Page 64
... TCLK. Writing a "1" selects the rising edge of the TCLK for sampling. D3 DATAP DATA Polarity: Writing a "0" to this bit selects transmit input and receive output data of the XRT83L30 to be active "High". Writing a "1" selects an active "Low" state. D2 Reserved D1 Reserved Software Reset µ ...
Page 65
... 128 128 256 256 XRT83L30 R R EGISTER ESET T V YPE ALUE R/W 0 R/W 0 CLKOUT MCLKRATE kHz 0 2048 1 1544 0 2048 1 1544 0 2048 1 1544 0 2048 1 1544 0 2048 1 1544 0 ...
Page 66
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 35: M ABLE D3 MCLKRATE Master Clock Rate Select: The state of this bit programs the Master Clock Synthesizer to generate the T1/ clock. The Master Clock Synthesizer will generate the E1 clock when MCLKRATE = “0”, and the T1/J1 clock when MCLKRATE = “1”. ...
Page 67
... ICROPROCESSOR EGISTER BIT DESCRIPTION SL_1 SL_0 Slicer Mode 0 0 Normal 0 1 Decrease by 5% from Normal 1 0 Increase by 5% from Normal 1 1 Normal EQG_1 EQG_0 Equalizer Gain 0 0 Normal 0 1 Reduce Gain Reduce Gain Normal 64 XRT83L30 R/W 0 R/W 0 R/W 0 R/W 0 ...
Page 68
... O E IGITAL NPUT AND UTPUT LECTRICAL =25°C, A UNLESS OTHERWISE SPECIFIED S M YMBOL IN VDD 3. 39: XRT83L30 P C OWER ONSUMPTION =25° NTERNAL MPEDANCE UNLESS OTHERWISE SPECIFIED T RANSFORMER R ATIO R T ECEIVER RANSMITTER 1:1 1:2 1:1 1:2 1:1 1:2 --- --- 65 REV. 1.0.1 C HARACTERISTICS NITS 3 ...
Page 69
... Hz 1 XRT83L30 T C EST ONDITIONS Cable attenuation @1024KHz ITU-G.775, ETSI 300 233 With nominal pulse amplitude of 3.0V Ω Ω for 120 and 2.37V for 75 applica- tion. With -18dB interference signal added. With nominal pulse amplitude of 3.0V Ω Ω ...
Page 70
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 41 ABLE VDD=3.3V±5 ARAMETER Receiver loss of signal: Number of consecutive zeros before RLOS is set Input signal level at RLOS RLOS Clear Receiver Sensitivity (Short Haul with cable loss) Receiver Sensitivity (Long Haul with cable loss) ...
Page 71
... UIpp - XRT83L30 T C EST ONDITIONS Ω Transformer with 1:2 ratio and 9.1 resistor in series with each end of pri- mary. ITU-G.703 ITU-G.703 Broad Band with jitter free TCLK applied to the input. ETSI 300 166, CHPTT T C EST ONDITIONS Tansformer with 1:2 ...
Page 72
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR F 26. ITU G.703 P IGURE V = 100% 50 ABLE Test Load Impedance Nominal Peak Voltage of a Mark Peak voltage of a Space (no Mark) Nominal Pulse width Ratio of Positive and Negative Pulses Imbalance T ULSE EMPLATE 269 ns ...
Page 73
... INIMUM CURVE T (UI) N IME ORMALIZED AMPLITUDE -0.77 -0.23 -0.23 -0.15 0.0 0.15 0.23 0.23 -0.45V 0.46 -0.45V 0.66 0.93 -0.05V 1.16 -0.05V ( ) NORMALIZED AMPLITUDE NTERFACE SOLATED ULSE ASK AND T (UI) IME -.05V -0.77 -.05V -0.39 0.5V -0.27 0.95V -0.27 0.95V -0.12 0.9V 0.0 0.5V 0.27 0.35 0.93 -0.2V 1.16 70 XRT83L30 C P ORNER OINTS M AXIMUM CURVE N ORMALIZED AMPLITUDE .05V .05V .8V 1.15V 1.15V 1.05V 1.05V -0.07V 0.05V 0.05V ...
Page 74
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T ABLE (T =25°C, VDD=3.3V±5 ARAMETER E1 MCLK Clock Frequency T1 MCLK Clock Frequency MCLK Clock Duty Cycle MCLK Clock Tolerance TCLK Duty Cycle Transmit Data Setup Time Transmit Data Hold Time TCLK Rise Time(10%/90%) ...
Page 75
... REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR F 29 IGURE ECEIVE LOCK AND UTPUT R DY RCLK RPOS or RNEG D T ATA IMING RCLK XRT83L30 RCLK F ...
Page 76
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PACKAGE DIMENSIONS A Seating Plane Note: The control dimension is the millimeter column SYMBOL α 64 LEAD THIN QUAD FLAT PACK ( 1.4 MM TQFP) REV. 3. ...
Page 77
... Rev. P1.3.0 Table 35: Microprocessor Register #17 Bit Description, edit E1 clock MCLKRATE= “0” and T1/J1 clock MCLKRATE=”1” . Rev. 1.0.0 Final Release. Rev. 1.0.1 Corrected package dimensions in ordering information table page 3. T 48. ABLE P ACKAGE 64 Pin TQFP Theta - J = 38° C XRT83L30 O R PERATING TEMPERATURE ANGE +85 C Theta J = 7° C/W C ...
Page 78
... XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...