xrt83l30 Exar Corporation, xrt83l30 Datasheet - Page 13

• Manufacturer Part Number: xrt83l30
• Description: Xrt83l30 -single-channel T1/e1/j1 Long-haul, Short-haul Line Interface Unit
• Manufacturer: Exar Corporation

CLOCK SYNTHESIZER
REV. 1.0.1
S
MCLKOUT
IGNAL
CLKSEL2
CLKSEL1
CLKSEL0
MCLKT1
N
AME
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
P
14
16
17
18
19
IN
#
T
YPE
O
I
I
T1 Master Clock Input
This signal is an independent 1.544MHz clock for T1 systems with required
accuracy of better than ±50ppm and duty cycle of 40% to 60%. MCLKT1
input is used in the T1 mode.
N
Synthesized Master Clock Output
This signal is the output of the Master Clock Synthesizer PLL which is at T1
or E1 rate based on the mode of operation.
Clock Select input for Master Clock Synthesizer pin 2
Clock Select input for Master Clock Synthesizer pin 1
Clock Select input for Master Clock Synthesizer pin 0
In Hardware mode, CLKSEL[2:0] are input signals to a programmable fre-
quency synthesizer that can be used to generate a master clock from an
external accurate clock source according to the following table. The
MCLKRATE control signal is generated from the state of EQC[4:0] inputs.
See
In Host mode, the state of these pins are ignored and the master frequency
PLL is controlled by the corresponding interface bits.
N
OTES
OTE
MCLKE1
(kHz)
2048
2048
2048
1544
1544
2048
Table 5
128
128
256
256
1. See MCLKE1 description for further explanation for the usage of
2. Internally pulled “Low” with a 50kΩ resistor.
16
16
56
56
64
64
: Internally pulled "Low" with a 50kΩ resistor.
8
8
:
this pin.
MCLKT1
(kHz)
2048
2048
1544
1544
1544
1544
for description of Transmit Equalizer Control bits.
10
X
X
X
X
X
X
X
X
X
X
X
X
CLKSEL2
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D
CLKSEL1
ESCRIPTION
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CLKSEL0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MCLKRATE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
XRT83L30
CLKOUT
(KHz)
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544