xrt83l30 Exar Corporation, xrt83l30 Datasheet - Page 66

• Manufacturer Part Number: xrt83l30
• Description: Xrt83l30 -single-channel T1/e1/j1 Long-haul, Short-haul Line Interface Unit
• Manufacturer: Exar Corporation

XRT83L30
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
R
EGISTER
10010
B
D3
D2
D1
D0
D7
D6
D5
D4
IT
A
#
DDRESS
MCLKRATE Master Clock Rate Select: The state of this bit programs the
TXONCNTL Transmit On Control.
TERCNTL
RXMUTE
GAUGE1
GAUGE0
EXLOS
N
ICT
AME
T
T
ABLE
ABLE
35: M
36: M
Master Clock Synthesizer to generate the T1/J1 or E1 clock. The
Master Clock Synthesizer will generate the E1 clock when
MCLKRATE = “0”, and the T1/J1 clock when MCLKRATE = “1”.
Receive Output Mute: Writing a "1" to this bit, mutes receive
outputs at RPOS/RDATA and RNEG/LCV pins to a "0" state.
N
Extended LOS: Writing a "1" to this bit extends the number of
zeros at the receive input before RLOS is declared to 4096 bits.
Writing a "0" reverts to the normal mode (175+75 bits for T1 and
32 bits for E1).
In-Circuit-Testing: Writing a "1" to this bit configures all the out-
put pins of the chip in "High" impedance mode for In-Circuit-Test-
ing. Setting ICT bit to “1” is equivalent to connecting the
Hardware ICT pin to ground.
Wire Gauge Selector Bit 1
This bit along with bit D6 are used to select wire gauge size as
shown in the table below.
Wire Gauge Selector Bit 0
See bit D7.
Transmit On/Off function to the TXON Hardware control pin.
N
Termination Control:
In Host mode, setting this bit to “1” transfers the control of the
RXTSEL to the RXTSEL Hardware control pin.
N
In Host mode, setting this bit to “1” transfers the control of the
OTE
OTE
OTE
ICROPROCESSOR
ICROPROCESSOR
: RCLK is not muted.
: This provides a faster On/Off capability for redundancy
: This provides a faster On/Off capability for redundancy
GAUGE1
application.
application.
0
0
1
1
GAUGE0
63
R
R
EGISTER
EGISTER
0
1
0
1
F
UNCTION
22 and 24 Gauge
22 Gauge
24 Gauge
26 Gauge
#17
#18
Wire Size
BIT DESCRIPTION
BIT DESCRIPTION
R
EGISTER
T
R/W
R/W
R/W
R/W
YPE
R/W
R/W
R/W
R/W
REV. 1.0.1
R
V
ALUE
ESET
0
0
0
0
0
0
0
0