xrt83l30 Exar Corporation, xrt83l30 Datasheet - Page 26

• Manufacturer Part Number: xrt83l30
• Description: Xrt83l30 -single-channel T1/e1/j1 Long-haul, Short-haul Line Interface Unit
• Manufacturer: Exar Corporation

XRT83L30
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
ARBITRARY PULSE GENERATOR
In T1 mode only, the arbitrary pulse generator divides the pulse into eight individual segments. Each segment
is set by a 7-Bit binary word by programming the appropriate register. This allows the system designer to set
the overshoot, amplitude, and undershoot for a unique line build out. The MSB (bit 7) is a sign-bit. If the sign-bit
is set to “1”, the segment will move in a positive direction relative to a flat line (zero) condition. If this sign-bit is
set to “0”, the segment will move in a negative direction relative to a flat line condition. A pulse with numbered
segments is shown in
N
TRANSMITTER
DIGITAL DATA FORMAT
Both the transmitter and receiver can be configured to operate in dual or single-rail data formats. This feature is
available under both Hardware and Host control modes. The dual or single-rail data format is determined by
the state of the SR/DR pin in Hardware mode or SR/DR interface bit in the Host mode. In single-rail mode,
transmit clock and NRZ data are applied to TCLK and TPOS/TDATA pins respectively. In single-rail and
Hardware mode the TNEG/CODE input can be used as the CODES function. With TNEG/CODE tied “Low”,
HDB3 or B8ZS encoding and decoding are enabled for E1 and T1 modes respectively. With TNEG/CODE tied
“High”, the AMI coding scheme is selected. In both dual or single-rail modes of operations, the transmitter
converts digital input data to a bipolar format before being transmitted to the line.
TRANSMIT CLOCK (TCLK) SAMPLING EDGE
Serial transmit data at TPOS/TDATA and TNEG/CODE are clocked into the XRT83L30 under the
synchronization of TCLK. With a “0” written to the TCLKE interface bit, or by pulling the TCLKE pin “Low”, input
data is sampled on the falling edge of TCLK. The sampling edge is inverted with a “1” written to TCLKE
interface bit, or by connecting the TCLKE pin “High”.
F
OTE
IGURE
: By default, the arbitrary segments are programmed to 0x00h. The transmitter output will result in an all zero pattern
to the line.
11. A
RBITRARY
Segment
1
2
3
4
5
6
7
8
Figure
P
ULSE
11.
S
Register
EGMENT
0xn8
0xn9
0xna
0xnb
0xnc
0xnd
0xne
0xnf
A
SSIGNMENT
1
2
3
23
4
5
6
7
8
REV. 1.0.1