ak4368 AKM Semiconductor, Inc., ak4368 Datasheet
ak4368
Related parts for ak4368
ak4368 Summary of contents
Page 1
... The integrated headphone amplifier features “pop-free” power-on/off, a mute control, and it delivers 50mW of power into 16Ω. The AK4368 is packaged in a 41-pin BGA package, deal for portable applications. ...
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... Boost PDN I2C CAD0/CSN Serial I/F SCL/CCLK SDA/CDTI MS0529-E-00 VCOC LIN MIN DAC (Lch) 3D Stereo Enhancement DAC (Rch) RIN Figure 1. Block Diagram - 2 - [AK4368EG] AVDD AVSS VCOM VCOM HDP MUTE HPL Amp LOUT 3DCAP1 3DCAP2 3DCAP3 ROUT HDP MUTE HPR Amp HVDD HVSS ...
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... ASAHI KASEI Ordering Information −30 ∼ +85°C AK4368EG AKD4368 Evaluation board for AK4368 Pin Layout HPL 5 MIN 4 RIN 3 VCOC 2 PVDD MS0529-E-00 41pin BGA (0.5mm pitch) AK4368EG Top View HPR HVDD AVDD VCOM ...
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... Power Supply Voltage Package 28QFN(5.2mm x 5.2mm) MS0529-E-00 AK4367 AK4368 27/26/19.8/19.68/19.2/ N/A 15.36/14.4/13/12/11.2896 MHz 8/11.025/12/16/22.05/24/3 N/A 2/44.1/48kHz 24bit Right justified 16/20/24bit Left justified N/A Available N/A Available N/A Available Mono Stereo 2 3-wire/I C +16dB (L+R)/2 LL, RR, (L+R)/2 50mW 50mW 2.2 ∼ 3.6V 1.6 ∼ 3.6V 20QFN(4.2mm x 4.2mm) 41BGA(4mm x 4mm [AK4368EG] 2006/07 ...
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... I Control Data Chip Select (I2C pin = “L”) Power-down & Reset F4 PDN I When “L”, the AK4368 is in power-down mode and is held in reset. The AK4368 should always be reset upon power-up. Capacitor Connect Pin 1 for 3D Stereo Enhancement G5 3DCAP1 O Connected to 3DCAP2 pin with 4.7nF capacitor in series. ...
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... Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name Analog LOUT, ROUT, MUTET, HPR, HPL, MIN, RIN, LIN Digital CAD0 MCKO MS0529-E-00 Function Setting These pins should be open. This pin should be connected to DVSS. This pin should be open [AK4368EG] 2006/07 ...
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... HVDD ∆GND1 - ∆GND2 - ∆GND3 - IIN - −0.3 VINA −0.3 VIND −30 Ta −65 Tstg Symbol min AVDD 1.6 DVDD 1.6 PVDD 1.6 HVDD 1.6 −0.3 AVDD−PVDD −0.3 AVDD−HVDD - 7 - [AK4368EG] max Units 4.6 V 4.6 V 4.6 V 4.6 V 0.3 V 0.3 V 0.3 V ±10 mA AVDD+0.3 or 4.6 V DVDD+0.3 or 4.6 V °C 85 °C 150 typ Max Units 2.4 3 ...
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... Note 9. Output voltage is proportional to AVDD voltage. Vout = 0.61 x AVDD(typ)@0dBFS. MS0529-E-00 ANALOG CHARACTERISTICS =16Ω and C =220µF. (Refer to Figure 48); unless otherwise specified min - - - 1.01 - =10kΩ) (Note 1.32 1 − [AK4368EG] typ Max Units 24 bit - −50 −40 dB − 0.3 0.5 dB 200 - ppm/° ...
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... Note 11. All digital input pins including clock pins (MCKI, BICK and LRCK) are held at DVSS. MS0529-E-00 min typ max 100 - 100 100 - 100 100 - 100 - 100 - 100 −1 0 −0.24 +0.76 +1.76 - 3.8 5.5 - 1.2 2 100 - 9 - [AK4368EG] Units - kΩ - kΩ - kΩ - kΩ - kΩ - kΩ - kΩ - kΩ - kΩ - kΩ - kΩ µA 2006/07 ...
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... MS0529-E-00 FILTER CHARACTERISTICS Symbol min 24 ∆ HPL/LOUT, RIN HPR/ROUT Boost Filter (fs=44.1kHz) 100 1000 Frequency [Hz] Figure 2. Boost Frequency (fs=44.1kHz [AK4368EG] typ max Units - 20.0 kHz 22.05 - kHz - - kHz ±0. 1/fs µ ±0 ±1 5. 10. ...
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... SDA pin: Iout=200µA) (SDA pin: Iout=3mA) Input Leakage Current Note 18. Only MCKI pin. (Figure 48) MS0529-E-00 DC CHARACTERISTICS Symbol Min VIH 70%DVDD VIH 80%DVDD VIL - VIL - VAC 0.4 VOH DVDD−0.2 VOL - VOL - Iin - - 11 - [AK4368EG] typ max Units - - 30%DVDD V - 20%DVDD Vpp - - 0.4 V ± ...
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... Units - 27 MHz - 12.288 MHz - - 44.1 48 kHz % - 12.288 MHz % - ...
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... PDN Pulse Width (Note 25) 2 Note 23 registered trademark of Philips Semiconductors. Note 24. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 25. The AK4368 can be reset by bringing PDN pin = “L” to “H” only upon power up. MS0529-E-00 Symbol min typ ...
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... MCKI Input MCKI tCLKH LRCK BICK tBCKH MCKO tH MS0529-E-00 Measurement Point 100kΩ DVSS DVSS Figure 3. MCKI AC Coupling Timing 1/fCLK tCLKL 1/fs tBCK tBCKL tL dMCK=tH/(tH+tL) or tL/(tH+tL) Figure 4. Clock Timing - 14 - [AK4368EG] 1/fCLK tACW tACW VAC VIH VIL VIH VIL VIH VIL 50% DVDD 2006/07 ...
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... ASAHI KASEI LRCK tBLR BICK SDATA Figure 5. Serial Interface Timing (Slave Mode) LRCK tMBLR BICK SDATA Figure 6. Serial Interface Timing (Master mode) MS0529-E-00 tLRB tSDS tSDH tSDH tSDS - 15 - [AK4368EG] VIH VIL VIH VIL VIH VIL 50%DVDD 50%DVDD VIH VIL 2006/07 ...
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... Figure 7. WRITE Command Input Timing Figure 8. WRITE Data Input Timing tHIGH tF tSU:DAT tSU:STA Start 2 Figure Bus Mode Timing tPD Figure 10. Power-down & Reset Timing - 16 - [AK4368EG] VIH VIL VIH VIL VIH A4 VIL tCSW VIH VIL tCSH VIH VIL VIH VIL ...
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... LRCK SDATA When the AK4368 is used in the master mode, LRCK and BICK pins are in a floating state until the M/S bit becomes “1”. LRCK and BICK pins of the AK4368 should be pulled-down or pulled- resistor (about 100kΩ) externally to avoid the floating state. ...
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... Table 3. LRCK input should be synchronized with MCKI or MCKO in slave mode. LRCK and BICK should always be present whenever the AK4368 is in normal operation mode (PMDAC bit = “1”). If these clocks are not provided, the AK4368 may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the AK4368 should be placed in power-down mode (PMDAC bit = “ ...
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... Slave Mode (M/S bit = “0”) Power Down (PMDAC bit= PMPLL bit= “0”) Input or fixed to “L” or “H” “L” Fixed to “L” or “H” externally Fixed to “L” or “H” externally - 19 - [AK4368EG] Type 4 47.9997kHz 23.9999kHz 11.9999kHz 31.9998kHz 15.9999kHz 7.9999kHz 44.0995kHz Default 22 ...
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... EXT mode (PMPLL bit = “0”: Default) The AK4368 can be placed in external clock mode (EXT mode) by setting the PMPLL bit to “0”. In EXT mode, the master clock can directly input to the DAC via the MCKI pin without going through the PLL. In this case, the sampling frequency and MCKI frequency can be selected by FS3-0 bits (refer to Table 6) ...
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... Fixed to “L” or “H” externally Fixed to “L” or “H” externally DR, S/N (BW=20kHz, A-weight) fs=8kHz fs=16kHz 256fs 56dB 75dB 512fs 75dB 90dB 90dB N [AK4368EG] MCKI 256fs 512fs 1024fs 256fs 512fs 1024fs 256fs Default 512fs 1024fs N/A 2006/07 ...
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... In all modes, the serial data is MSB first and 2’s complement format. When master mode and BICK=32fs(BF bit = “0”), the AK4368 cannot be set to Mode 1 or Mode 2. Mode ...
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... Don’ care Don’ care [AK4368EG] Rch Don’ care Don’ care Don’ care Rch Don’ care Don’t ...
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... ALC Limiter ATT Step ALC Output ≥ ALC Output ≥ ALC Output ≥ −6.0dBFS 0dBFS +6dBFS Table 13. ALC Limiter ATT Step - 24 - [AK4368EG] fs=32kHz fs=44.1kHz fs=48kHz 32ms 23ms 21ms 64ms 46ms 43ms 128ms 93ms 85ms - - - ALC Output ≥ ...
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... Table 15. Reference Level for ALC Recovery operation MS0529-E-00 RATT GAIN STEP 0 1 Default 1 2 Table 14. ALC Recovery GAIN Step REF7-0 GAIN(dB) FFH : Reserved C2H C1H +18.0 C0H +17.625 BFH +17. 92H +0.375 91H 0 Default −0.375 90H : : −11.25 73H −11.625 72H −12.0 71H 70H : Reserved 00H - 25 - [AK4368EG] 2006/07 ...
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... Enable Table 16. Example of the ALC setting Example: Recovery Cycle = 46ms@44.1kHz Limiter and Recovery Step = 1 Maximum Gain = +18dB ALC bit = “1” [AK4368EG] fs=44.1kHz Data Operation 01 46ms C1H +18dB 00 1 step 0 1 step 1 Enable (1) Addr=0AH, Data=C1H ...
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... ASAHI KASEI Digital Attenuator The AK4368 has a channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before the D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to −127dB or MUTE) for each channel (Table 17). At DATTC bit = “1”, ATTL7-0 bits control both channel’s attenuation levels. At DATTC bit = “0”, ATTL7-0 bits control the left channel level and ATTR7-0 bits control the right channel level ...
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... The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinued and it is returned to the ATT level by the same cycle. MS0529-E-00 ATS bit (1) (1) GD (2) Figure 20. Soft Mute Function - 28 - [AK4368EG] (3) GD 2006/07 ...
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... System Reset The AK4368 should be reset once by bringing PDN pin “L” upon power-up. After exiting reset, VCOM, DAC, HPL, HPR, LOUT and ROUT switch to the power-down state. The contents of the control register are maintained until the reset is completed. The DAC exits reset and power down states by MCKI after the PMDAC bit is changed to “1”. The DAC is in power-down mode until MCKI is input ...
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... HVSS, some pop noise may occur. MS0529-E-00 70k x C (typ) 60k x C (typ) Table 22. Headphone-Amp Rise/Fall Time = 70k x 1µ = 70ms(typ 60k x 1µ = 60ms(typ (1) (2) ( [AK4368EG (4) = 70k x r 2006/07 ...
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... R C Headphone 16Ω Output Power [mW] fc [Hz] HPG=0, 0dB BOOST=MIN 2.4V 3. 50k), the DAC path gain is +6.76dB(typ). 1 100k(typ) 100k(typ) 100k(typ) − [AK4368EG HPG=1, −4.8dB 3.3V 3. 1.09R 2 − HPL/HPR pin + HP-Amp 2006/07 = ...
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... ATTS3-0 bits are changed. LMUTE 0 1 Table 24. LOUT/ROUT Volume ATT values (x: Don’t care) MS0529-E-00 100k(typ) 100k(typ) 100k(typ) − ATTS3-0 Attenuation 0FH 0dB −2dB 0EH −4dB 0DH −6dB 0CH : : : : −28dB 01H −30dB 00H X MUTE - 32 - [AK4368EG] = 50k − LOUT/ROUT pin + Default 2006/07 ...
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... ASAHI KASEI 3D Stereo Enhancement AK4368 features a 3D stereo enhancement function. 3D1-0 bits control the power management of the 3D function block (Table 25), and DP1-0 bits set the 3D depth (Table 26). 3D1-0 and MUTEN bits should not be changed to avoid pop noise for 50ms after 3D1-0 bits are changed. ...
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... MS0529-E-00 Don’t care Don’t care Normal Operation PD “10”( “00” FFH(0dB) 00H(MUTE) (9) GD (10) 1061/fs (9) (10) (7) (8) = 70ms(typ 60ms(typ [AK4368EG] (11) Don’t care Normal Operation PD (4) >0 (5) >0 “10” “00” (6) >2ms, or >50ms FFH(0dB) 00H(MUTE) (9) (10) (9) (10) (8) 2006/07 ...
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... The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). MS0529-E-00 Don’t care (6) Don’t care (5) >0 (at 3D OFF) (5) >0 (at 3D ON) Normal Operation “01”(3D ON) “00” FFH(0dB) 00H(MUTE) 0FH(0dB) (8) GD (9) 1061/fs (8) (9) (7) (7) (Hi- [AK4368EG] PD Normal Operation “01” FFH(0dB) (8) (9) (7) 2006/07 ...
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... PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to HVSS. After that, LINHL, MINHL, RINHR and MINHR bits should be changed to “0”. MS0529-E-00 Don’t care (5) >0s “01”, “10” or “11” (3D ON) “00” (6) >2ms(at 3D OFF), >50ms(at 3D ON) (Hi-Z) (7) (8) = 70ms(typ 60ms(typ [AK4368EG] “01”, “10” or “11” (6) >2ms or >50ms (7) 2006/07 ...
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... When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. MS0529-E-00 Don’t care (5) >0s “01”, “10” or “11” (3D ON) “00” (6) >2ms(at 3D OFF), >50ms(at 3D ON) (Hi-Z) 0FH(0dB) (7) (7) (Hi- [AK4368EG] “01”, “10” or “11” (6) >2ms or >50ms (7) 2006/07 ...
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... Unstable Unstable Normal Operation PD Unstable (6) >0 (7) >0 “10”( “00” FFH(0dB) 00H(MUTE) (11) (12) (10) (9) = 70ms(typ 60ms(typ [AK4368EG] (13) Don’t care Don’t care Normal Operation PD Don’t care “10” “00” (8) >2ms, or >50ms FFH(0dB) 00H(MUTE) (11) (12) (11) (12) (10) 2006/07 ...
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... Don’t care Don’t care Unstable (5) Unstable Unstable Normal Operation PD Unstable (6) >0 “01”(3D ON) (8) >0 (at 3D OFF) (8) >0 (at 3D ON) FFH(0dB) 00H(MUTE) 0FH(0dB) (10) GD (11) 1061/fs (10) (11) (9) (9) (Hi- [AK4368EG] (4) ~20ms Normal Operation (7) >0 “00” “01” (8) >0 (at 3D OFF) (8) >0 (at 3D ON) FFH(0dB) (10) (11) (9) 2006/07 ...
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... PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to HVSS. After that, LINHL, MINHL, RINHR and MINHR bits should be changed to “0”. MS0529-E-00 Don’t care (5) >0s “01”, “10” or “11” (3D ON) “00” (6) >2ms(at 3D OFF), >50ms(at 3D ON) (Hi-Z) (7) (8) = 70ms(typ 60ms(typ [AK4368EG] “01”, “10” or “11” (6) >2ms or >50ms (7) 2006/07 ...
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... When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. MS0529-E-00 Don’t care (5) >0s “01”, “10” or “11” (3D ON) “00” (6) >2ms(at 3D OFF), >50ms(at 3D ON) (Hi-Z) 0FH(0dB) (7) (7) (Hi- [AK4368EG] “01”, “10” or “11” (6) >2ms or >50ms (7) 2006/07 ...
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... Unstable Unstable Normal Operation PD Unstable (6) >0 (7) >0 “10”( “00” FFH(0dB) 00H(MUTE) (11) (12) (10) (9) = 70ms(typ 60ms(typ [AK4368EG] (13) Don’t care Don’t care Normal Operation PD Don’t care “10” “00” (8) >2ms, or >50ms FFH(0dB) 00H(MUTE) (11) (12) (11) (12) (10) 2006/07 ...
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... Don’t care Don’t care Unstable (5) Unstable Unstable Normal Operation PD Unstable (6) >0 “01”(3D ON) (8) >0 (at 3D OFF) (8) >0 (at 3D ON) FFH(0dB) 00H(MUTE) 0FH(0dB) (10) GD (11) 1061/fs (10) (11) (9) (9) (Hi- [AK4368EG] (4) ~20ms Normal Operation (7) >0 “00” “01” (8) >0 (at 3D OFF) (8) >0 (at 3D ON) FFH(0dB) (10) (11) (9) 2006/07 ...
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... PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to HVSS. After that, LINHL, MINHL, RINHR and MINHR bits should be changed to “0”. MS0529-E-00 Don’t care (5) >0s “01”, “10” or “11” (3D ON) “00” (6) >2ms(at 3D OFF), >50ms(at 3D ON) (Hi-Z) (7) (8) = 70ms(typ 60ms(typ [AK4368EG] “01”, “10” or “11” (6) >2ms or >50ms (7) 2006/07 ...
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... When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. MS0529-E-00 Don’t care (5) >0s “01”, “10” or “11” (3D ON) “00” (6) >2ms(at 3D OFF), >50ms(at 3D ON) (Hi-Z) 0FH(0dB) (7) (7) (Hi- [AK4368EG] “01”, “10” or “11” (6) >2ms or >50ms (7) 2006/07 ...
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... CSN 0 1 CCLK CDTI C1 C0 R/W Figure 38. 3-wire Serial Control I/F Timing MS0529-E- C1-C0: Chip Address (Fixed to “01”) R/W: READ/WRITE (Fixed to “1”, Write only) A4-A0: Register Address D7-D0: Control Data - 46 - [AK4368EG 2006/07 ...
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... STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 45). The AK4368 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4368 generates an acknowledgement and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred ...
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... ASAHI KASEI (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4368. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. ...
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... MASTER S START CONDITION SDA SCL MS0529-E-00 Figure 45. START and STOP Conditions Figure 46. Acknowledge on the I C-Bus data line change stable; of data data valid allowed 2 Figure 47. Bit Transfer on the I C-Bus - 49 - [AK4368EG] P stop condition not acknowledge acknowledge 8 9 clock pulse for acknowledgement 2006/07 ...
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... ATTR4 0 HPG MINHR MINHL 0 LOG MINR MINL REF7 REF6 REF5 REF4 0 0 ALC ROTM1 [AK4368EG PMHPR PMHPL PMDAC PMVCM PLL3 PLL1 PLL0 PLL2 BF PS0 PS1 MCKO LRP DIF2 DIF1 DIF0 BST1 BST0 DEM1 DEM0 ATTL3 ...
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... PLL mode: Note 26. Type 1-4 frequency is indicated in Table 2. Table 1 EXT mode: Disable MS0529-E- PMPLL PMLO MUTEN RD R/W R/W R FS3 FS2 FS1 FS0 R/W R/W R/W R [AK4368EG PMHPR PMHPL PMDAC PMVCM R/W R/W R/W R PLL3 PLL2 PLL1 PLL0 R/W R/W R/W R 2006/07 ...
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... Invert MONO1-0: Mixing Select (Table 21) Default: “00” (LR) MS0529-E- M/S MCKAC RD RD R/W R MONO1 MONO0 BCKP RD R/W R/W R [AK4368EG PS0 PS1 MCKO R/W R/W R/W R LRP DIF2 DIF1 DIF0 R/W R/W R/W R 2006/07 ...
Page 53
... Default: “00H” (MUTE) MS0529-E- ATS DATTC LMUTE SMUTE R/W R/W R/W R ATTL6 ATTL5 ATTL4 ATTR6 ATTR5 ATTR4 R/W R/W R/W R [AK4368EG BST1 BST0 DEM1 DEM0 R/W R/W R/W R ATTL3 ATTL2 ATTL1 ATTL0 ATTR3 ATTR2 ATTR1 ATTR0 R/W R/W R/W R ...
Page 54
... ON MINHR: Input signal to MIN pin is added to the right channel of the headphone-amp. 0: OFF (Default HPG: DAC HPL/R Gain 0: 0.76dB (Default) 1: +6.76dB MS0529-E- HPG MINHR MINHL RD R/W R/W R [AK4368EG RINHR LINHL DACHR DACHL R/W R/W R/W R 2006/07 ...
Page 55
... Setting of ATTS3-0 bits is enabled at LMUTE bit is “0”. MS0529-E- LOG MINR MINL RD R/W R/W R [AK4368EG RINR LINL DACR DACL R/W R/W R/W R ATTS3 ATTS2 ATTS1 ATTS0 R/W R/W R/W R 2006/07 ...
Page 56
... R/W R/W R ALC ROTM1 RD RD R/W R [AK4368EG REF3 REF2 REF1 REF0 R/W R/W R/W R ROTM0 LMAT1 LMAT0 RATT R/W R/W R/W R DP1 DP0 3D1 3D0 ...
Page 57
... Do not let digital input pins float. - When the AK4368 is in EXT mode (PMPLL bit = “0”), a resistor and capacitor for the VCOC pin is not needed. - When the AK4368 is in PLL mode (PMPLL bit = “1”), a resistor and capacitor for the VCOC pin is shown in Note 26 ...
Page 58
... Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. When AVDD and HVDD are supplied separately, AVDD is powered-up at the same time or earlier than HVDD. When the AK4368 is powered-down, HVDD is powered-down at the same time or later than AVDD. The power up sequence of PVDD is not critical ...
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... ASAHI KASEI 4.0 ± 0.1 Package & Lead frame material Package molding compound: Interposer material: Solder ball material: MS0529-E-00 PACKAGE 41 - φ 0.3 ± 0.05 φ 0. 0.08 S Epoxy BT resin SnAgCu - 59 - [AK4368EG 0.5 0.5 3.0 2006/07 ...
Page 60
... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0529-E-00 MARKING 4368 XXXX XXXX: Date code (4 digit) Pin #1 indication Revision History Page Contents IMPORTANT NOTICE - 60 - [AK4368EG] 2006/07 ...