ak4368 AKM Semiconductor, Inc., ak4368 Datasheet - Page 38

• Manufacturer Part Number: ak4368
• Description: Dac With Built-in Pll & Hp-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
1) DAC → HP-Amp
(1) PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM, PMPLL, PMDAC and MCKO bits should be changed to “1” after PDN pin goes “H”.
(3) The PLL executes when the system clock is input to MCKI.
(4) The PLL lock time is referred to Note 26. Type 1-4 frequency is indicated in Table 2.
(5) Table 1. After the PLL is locked, the MCKO pin outputs the master clock.
(6) The clocks (BICK, LRCK) generated by MCKO are needed to operate the DAC. When the PMDAC bit = “0”, these
(7) DACHL and DACHR bits should be changed to “1” after the PLL is locked.
(8) When the 3D function is used, 3D1-0 bits should be changed to “10” after DACHL and DACHR bits are changed to
(9) When the 3D function is not used, PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case
(10) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
(11) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
(12) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499µs@fs=44.1kHz).
(13) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
(14) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”).
MS0529-E-00
Power-Up/Down Sequence (PLL Slave mode)
MCKI pin
DAC Internal
SDTI pin
PMHPL,
PMHPR bits
MUTEN bit
ATTL7-0
ATTR7-0 bits
HPL/R pin
clocks can be stopped. The headphone-amp can operate without these clocks.
“1”.
external capacitance at VCOM pin is 2.2µF) after the DACHL and DACHR bits are changed to “1”. When the 3D
function is used, PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 50ms after 3D1-0 bits are
changed to “10”.
VCOM/2 is t
VCOM/2 is t
PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to HVSS. After that, the
DACL/DACR bits should be changed to “0” and 3D1-0 bits should be changed to “00”.
Power Supply
PDN pin
PMVCM, PMPLL,
PMDAC, MCKO bits
MCKO pin
BICK,
LRCK pins
DACHL,
DACHR bits
3D1-0 bits
(when 3D is used)
State
r
f
Figure 30. Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z)
= 70k x C(typ). When C=1µF, t
= 60k x C(typ). When C=1µF, t
“00”(3D OFF)
Don’t care
PD
Unstable
Don’t care
Don’t care
(1)
>150ns
Unstable
Unstable
00H(MUTE)
(2) >0
(3)
(4) ~20ms
(5)
(9)
(6) >0
(7) >0
(8) >2ms(at 3D OFF), >50ms(at 3D ON)
(11) GD (12) 1061/fs
Normal Operation
FFH(0dB)
“10”(3D ON )
r
f
= 70ms(typ).
= 60ms(typ).
(11) (12)
- 38 -
Unstable
(10)
00H(MUTE)
Don’t care
Don’t care
Unstable
Unstable
PD
Unstable
“00”
(4) ~20ms
(9)
(6) >0
(7) >0
(8) >2ms, or >50ms
Normal Operation
(11) (12)
FFH(0dB)
“10”
(11) (12)
00H(MUTE)
Don’t care
Don’t care
Don’t care
(10)
[AK4368EG]
“00”
PD
2006/07
(13)