xr16m670 Exar Corporation, xr16m670 Datasheet - Page 36

• Manufacturer Part Number: xr16m670
• Description: 1.62v To 3.63v High Performance Uart With 32-byte Fifo
• Manufacturer: Exar Corporation

XR16M670
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
EMSR[2]: Send TX Immediately
•
•
EMSR[3]: Invert RTS in RS485 mode
•
•
EMSR[5:4]: Reserved
EMSR[6]: LSR Interrupt Mode
•
•
EMSR[7]: Xoff/Special character Interrupt Mode Select
This bit selects how the Xoff and Special character interrupt is cleared. The XON interrupt can only be cleared
by reading the ISR register.
•
•
These registers make-up the value of the baud rate divisor. The M670 has different DLL, DLM and DLD for
transmitter and receiver. It provides more convenience for the transmitter and receiver to transmit data with
different rate. The M670 uses DLD[7:6] to select TX or RX. Then it provides DLD[5:0] to select the sampling
frequency and fractional baud rate divisor. The concatenation of the contents of DLM and DLL gives the 16-bit
divisor value. The value is added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. See
Baud Rate Generator with Fractional Divisor” on page 11.
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See
4.13
Logic 0 = Do not send TX immediately (default).
Logic 1 = Send TX immediately. When FIFO is enabled and this bit is set, the next data will be to the TX shift
register. Thus, the data will be sent out immediately instead of queuing in the FIFO. Every time, only 1 byte
will be send out. Once this byte has been sent out, the EMSR[2] will go back to 0 automatically. If more than
1 byte will be sent out, EMSR[2] needs to be set to 1 for each byte.
Logic 0 = RTS# output is a logic 0 during TX and a logic 1 during RX (default).
Logic 1 = RTS# output is a logic 1 during TX and a logic 0 during RX.
Logic 0 = LSR Interrupt Delayed (default). LSR bits 2, 3, and 4 will generate an interrupt when the character
with the error is in the RHR.
Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is
received into the FIFO.
Logic 0 = Xoff interrupt is cleared by either reading ISR register or when an XON character is received.
Special character interrupt is cleared by either reading ISR register or when next character is received.
(default).
Logic 1 = Xoff/Special character interrupt can only be cleared by reading the ISR register.
Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
DLD[5]
0
0
1
T
ABLE
13: S
AMPLING
DLD[4]
36
X
Table 13
0
1
R
ATE
below and
S
ELECT
See ”Section 2.7, Programmable
Table 13
S
AMPLING
16X
8X
4X
R
below.
ATE
REV. 1.0.0