xr16m670 Exar Corporation, xr16m670 Datasheet - Page 37

• Manufacturer Part Number: xr16m670
• Description: 1.62v To 3.63v High Performance Uart With 32-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.0
DLD[6]: Independent BRG enable
•
•
DLD[7]: BRG select
When DLD[6] = 1, this bit selects whether the values written to DLL, DLM and DLD[5:0] will be for the Transmit
Baud Rate Generator or the Receive Baud Rate Generator. When DLD[6] = 0 (same Baud Rate Generator
used for both TX and RX), this bit must be a logic 0 to properly write to the appropriate DLL, DLM and
DLD[5:0]. .
This register replaces SPR (during a read) and is accessible when FCTR[6] = 1. This register is also
accessible when LCR = 0xBF. It is suggested to read the FIFO Level Count Register at the Scratchpad
Register location when FCTR bit-6 = 1. See
FC[7:0]: RX/TX FIFO Level Count
Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter
FIFO (FCTR[7] = 1) can be read via this register. Reading this register is not recommended when transmitting
or receiving data.
FCTR[1:0]: Reserved
FCTR[2]: IrDa RX Inversion
•
•
FCTR[3]: Auto RS-485 Direction Control
•
•
FCTR[5:4]: Reserved
4.14
4.15
Logic 0 = The Transmitter and Receiver uses the same Baud Rate Generator. (default).
Logic 1 = The Transmitter and Receiver uses different Baud Rate Generators. Use DLD[7] for selecting
which baud rate generator to configure.
Logic 0 = Select RX input as encoded IrDa data (Idle state will be LOW).
Logic 1 = Select RX input as inverted encoded IrDa data (Idle state will be HIGH).
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
becomes empty and transmit shift register is shifting data out.
Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its
output logic state from LOW to HIGH one bit time after the last stop bit of the last character is shifted out.
Also, the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The
RTS# output pin will automatically return to a LOW when a data byte is loaded into the TX FIFO. However,
RTS# behavior can be inverted by setting EMSR[3] = 1.
DLD[7]
0
0
1
1
RX/TX FIFO Level Count Register (FC) - Read-Only
Feature Control Register (FCTR) - Read/Write
DLD[6]
0
1
1
0
Writing to DLL, DLM and DLD[5:0] has no effect on BRG used by the TX and RX.
Writing to DLL, DLM and DLD[5:0] configures the BRG for both the TX and RX.
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
Writing to DLL, DLM and DLD[5:0] configures the BRG for TX.
Writing to DLL, DLM and DLD[5:0] configures the BRG for RX.
T
Table
ABLE
Transmitter and Receiver uses different BRGs.
Transmitter and Receiver uses different BRGs.
Transmitter and Receiver uses same BRG.
Transmitter and Receiver uses same BRG.
14: BRG S
12.
37
ELECT
BRG
XR16M670