xr16m890 Exar Corporation, xr16m890 Datasheet - Page 13

• Manufacturer Part Number: xr16m890
• Description: Uart With 128-byte Fifo And Integrated Level Shifters
• Manufacturer: Exar Corporation

REV. P1.1.1
The RESET# input resets the internal registers and the serial interface outputs to their default state (see
Table
device. Following a power-on reset or an external reset, the M890 is software compatible with previous
generation of UARTs.
The M890 can accept and withstand 5V signals on the inputs without any damage. But note that if the supply
voltage for the M890 is at the lower end of the supply voltage range (ie. 1.8V), its V
to meet the requirements of the V
not 5 volt tolerant.
The M890 has a set of 16550 compatible registers for controlling, monitoring and data loading and unloading.
These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER),
a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status and control
registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible
scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the M890 offers enhanced feature registers (EFR, Xon1/
Xoff 1, Xon2/Xoff 2, DLD, FCTR, EMSR, FC and TRIG, SFR, SHR, GPIOINT, GPIO3T, GPIOINV, GPIOSEL)
that provide automatic RTS and CTS hardware flow control, automatic Xon/Xoff software flow control, 9-bit
(Multidrop) mode, auto RS-485 half duplex control, different baud rate for TX and RX and fractional baud rate
generator. All the register functions are discussed in full detail later in
REGISTERS” on page
The interrupt outputs change according to the operating mode and enhanced features setup.
summarize the operating behavior for the transmitter and receiver. Also see
1.3
1.4
1.5
1.6
(Intel or VLIO Mode)
(Intel or VLIO Mode)
19). An active low pulse of longer than 40 ns duration will be required to activate the reset function in the
(Motorola Mode)
(Motorola Mode)
Device Reset
5-Volt Tolerant Inputs
Internal Registers
INT Ouput
IRQ# Pin
IRQ# Pin
INT Pin
INT Pin
27.
T
LOW = One byte in THR
HIGH = THR empty
HIGH = One byte in THR
LOW = THR empty
HIGH = One byte in RHR
LOW = RHR empty
HIGH = One byte in THR
LOW = RHR empty
ABLE
T
ABLE
FCR B
FCR B
IH
1: I
of a CPU or a serial transceiver that is operating at 5V. Caution: XTAL1 is
2: I
D
D
NTERRUPT
IT
ISABLED
IT
ISABLED
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
-0 = 0 (FIFO
NTERRUPT
-0 = 0 (FIFO
)
)
P
PRELIMINARY
IN
P
IN
O
13
PERATION FOR
O
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
HIGH = FIFO above trigger level
LOW = FIFO below trigger level or FIFO empty
PERATION FOR
LOW = FIFO below trigger level
HIGH = FIFO above trigger level or RX Data Timeout
HIGH = FIFO above trigger level
LOW = FIFO above trigger level or RX Data Timeout
FCR B
T
FCR B
RANSMITTER
R
ECEIVER
IT
IT
“Section 2.0, UART INTERNAL
Figure 26
-0 = 1 (FIFO E
-0 = 1 (FIFO E
OH
may not be high enough
through 29.
NABLED
NABLED
XR16M890
Table 1 and 2
)
)