xr16m890 Exar Corporation, xr16m890 Datasheet - Page 47

• Manufacturer Part Number: xr16m890
• Description: Uart With 128-byte Fifo And Integrated Level Shifters
• Manufacturer: Exar Corporation

REV. P1.1.1
FCTR[3]: Auto RS-485 Direction Control
•
•
FCTR[5:4]: Transmit/Receive Trigger Table Select
See
FCTR[6]: Scratchpad Swap
•
•
FCTR[7]: Programmable Trigger Register Select
•
•
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
3.19
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
becomes empty and transmit shift register is shifting data out.
Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its
output logic state from LOW to HIGH one bit time after the last stop bit of the last character is shifted out.
Also, the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The
RTS# output pin will automatically return to a LOW when a data byte is loaded into the TX FIFO. However,
RTS# behavior can be inverted by setting EMSR[3] = 1.
Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced
Mode Select Register is selected when it is written into.
Logic 0 = Registers TRG and FC selected for RX.
Logic 1 = Registers TRG and FC selected for TX.
Table 17
Enhanced Feature Register (EFR) - Read/Write
for more details.
FCTR
B
IT
0
0
1
1
-5
T
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
ABLE
FCTR
B
IT
0
1
0
1
-4
17: T
Table
PRELIMINARY
RIGGER
18). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
47
T
Table-C (TX/RX)
Table-D (TX/RX)
Table-A (TX/RX)
Table-B (TX/RX)
ABLE
T
ABLE
S
ELECT
XR16M890