xr16m890 Exar Corporation, xr16m890 Datasheet - Page 28

• Manufacturer Part Number: xr16m890
• Description: Uart With 128-byte Fifo And Integrated Level Shifters
• Manufacturer: Exar Corporation

A
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
A2-A0
DDRESS
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1
T
ABLE
GPIOLVL RD/WR
N
RHR
MCR
MSR
THR
FCR
SHR
SPR
LCR
LSR
SFR
R
IER
ISR
AME
EG
7: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR Divisor
RD/WR
RD/WR
W
R
WR
WR
WR
WR
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
Enabled
RS-485
Enable
Trigger
Enable
Global
Bit-15/
FIFOs
CTS#
Setup
B
Pres-
BRG
caler
Error
Input
Bit-7
Bit-7
Bit-3
CD#
Bit-7
Bit-7
9-bit
Int.
TX
IT
0/
0/
-7
RX FIFO
IR Mode
Enabled
ENable
RS-485
Trigger
Enable
Set TX
THR &
Enable
Bit-14/
FIFOs
Empty
Break
Setup
RTS#
mode
B
Input
Bit-6
Bit-6
Bit-2
Bit-6
Bit-6
TSR
9-bit
RI#
Int.
IT
0/
0/
16C550 Compatible Registers
-6
Interrupt
TX FIFO
XonAny
PRELIMINARY
Xoff Int.
RS-485
Disable
Enable
Trigger
Bit-13/
Empty
Setup
DSR#
Parity
B
Input
Bit-5
Bit-5
RTS
CTS
THR
Bit-1
Bit-5
Bit-5
Set
RX
IT
0/
0/
0/
-5
28
RX Break RX Fram-
TX FIFO
Interrupt
Lopback
Internal
RS-485
Disable
Enable
Trigger
Enable
Bit-12/
Setup
Sleep
Mode
Parity
CTS#
B
Even
Input
Bit-4
Bit-4
Bit-0
Bit-4
Bit-4
Xoff
TX
IT
0/
0/
-4
S
HADED BITS ARE ENABLED WHEN
Int Enable
Wake up
INT Out-
ing Error
Stat. Int.
Hystere-
RS-485
Modem
(OP2#)
Enable
Source
Enable
Enable
Bit-11/
Parity
Delay
B
Bit-3/
Delta
Bit-3
Bit-3
Bit-3
Bit-3
CD#
Bit-3
Bit-3
Fast
INT
put
sis
IT
IR
-3
RX Line
RS-485
Enable
Source
Enable
Hyster-
Bit-10/
OP1#/
Select
Reset
GPIO
Parity
Delay
GPIO
B
Delta
FIFO
Error
Bit-2
Bit-2
Bit-2
Bit-2/
Bit-2
Bit-2
Bit-2
Stat.
Stop
esis
INT
Bits
INT
RI#
Int.
RX
TX
IT
-2
RS-485
Source
Control
Enable
Length
Output
Hyster-
Empty
[15:8]/
Select
Reset
DSR#
RTS#
Over-
Delay
GPIO
B
Word
Delta
Bit-9/
FIFO
Error
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1/
Bit-1
Bit-1
Bit-1
[7:0]
esis
INT
RX
RX
run
TX
Int
IT
-1
EFR B
RX Data
RX Data
Hystere-
RS-485
Control
Access
Enable
Source
Enable
Length
Output
Ready
FIFOs
DTR#
Delay
CTS#
GPIO
Word
B
Bit-0/
Delta
Bit-8/
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
INT
Int.
sis
IT
-0
IT
-4=1
REV. P1.1.1
if EFR[4]=1
if EFR[4]=0
LCR≠0xBF
LCR≠0xBF
LCR≠0xBF
FCTR[6]=0
LCR≠0xBF
FCTR[6]=0
LCR[7] = 0
LCR[7] = 0
C
SFR[0]=0
SFR[0]=1
OMMENT
or