sc16c752 NXP Semiconductors, sc16c752 Datasheet - Page 5

• Manufacturer Part Number: sc16c752
• Description: Dual Uart With 64-byte Fifo
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 2:
9397 750 11635
Product data
Symbol
CTSA, CTSB
D0-D4,
D5-D7
DSRA, DSRB
DTRA, DTRB
GND
INTA, INTB
IOR
IOW
NC
OPA, OPB
RESET
RIA, RIB
Pin description
Pin
38, 23
44-48,
1-3
39, 20
34, 35
17
30, 29
19
15
12, 24,
25, 37
32, 9
36
41, 21
…continued
Type
I
I/O
I
O
I
O
I
I
-
O
I
I
Description
Clear to Send (Active-LOW). These inputs are associated with individual UART
channels A and B. A logic 0 (LOW) on the CTS pins indicates the modem or data set is
ready to accept transmit data from the SC16C752. Status can be tested by reading
MSR[4]. These pins only affect the transmit and receive operations when Auto-CTS
function is enabled via the Enhanced Feature Register EFR[7] for hardware flow
control operation.
Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for transferring
information to or from the controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
Data Set Ready (Active-LOW). These inputs are associated with individual UART
channels A and B. A logic 0 (LOW) on these pins indicates the modem or data set is
powered-on and is ready for data exchange with the UART. The state of these inputs is
reflected in the modem status register (MSR).
Data Terminal Ready (Active-LOW). These outputs are associated with individual
UART channels A and B. A logic 0 (LOW) on these pins indicates that the SC16C752
is powered-on and ready. These pins can be controlled via the modem control register.
Writing a logic 1 to MCR[0] will set the DTR output to logic 0 (LOW), enabling the
modem. The output of these pins will be a logic 1 after writing a logic 0 to MCR[0], or
after a reset.
Signal and power ground.
Interrupt A and B (Active-HIGH). These pins provide individual channel interrupts
INTA and INTB. INTA and INTB are enabled when MCR[3] is set to a logic 1, interrupt
sources are enabled in the interrupt enable register (IER). Interrupt conditions include:
receiver errors, available receiver buffer data, available transmit buffer space, or when
a modem status flag is detected. INTA, INTB are in the high-impedance state after
reset.
Input/Output Read strobe (Active-LOW). A HIGH-to-LOW transition on IOR will load
the contents of an internal register defined by address bits A0-A2 onto the SC16C752
data bus (D0-D7) for access by external CPU.
Input/Output Write strobe (Active-LOW). A LOW-to-HIGH transition on IOW will
transfer the contents of the data bus (D0-D7) from the external CPU to an internal
register that is defined by address bits A0-A2 and CSA and CSB.
Not connected.
User defined outputs. This function is associated with individual channels A and B.
The state of these pins is defined by the user through the software settings of MCR[3].
INTA-INTB are set to active mode and OPA-OPB to a logic 0 when MCR[3] is set to a
logic 1. INTA-INTB are set to the 3-State mode and OPA-OPB to a logic 1 when
MCR[3] is set to a logic 0. The output of these two pins is HIGH after reset.
Reset. This pin will reset the internal registers and all the outputs. The UART
transmitter output and the receiver input will be disabled during reset time. RESET is
an active-HIGH input.
Ring Indicator (Active-LOW). These inputs are associated with individual UART
channels, A and B. A logic 0 on these pins indicates the modem has received a ringing
signal from the telephone line. A LOW-to-HIGH transition on these input pins
generates a modem status interrupt, if enabled. The state of these inputs is reflected
in the modem status register (MSR).
Rev. 04 — 20 June 2003
Dual UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C752
5 of 47