sc16c752 NXP Semiconductors, sc16c752 Datasheet - Page 8

• Manufacturer Part Number: sc16c752
• Description: Dual Uart With 64-byte Fifo
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 11635
Product data
Fig 4. RTS functional timing.
Fig 5. CTS functional timing.
(1) N = receiver FIFO trigger level.
(2) The two blocks in dashed lines cover the case where an additional byte is sent, as described in
(1) When CTS is LOW, the transmitter keeps sending serial data out.
(2) When CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current
(3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.
byte, but is does not send the next byte.
RTS
IOR
RX
CTS
TX
6.2.1 Auto-RTS
6.2.2 Auto-CTS
START
Auto-RTS data flow control originates in the receiver block (see
diagram.” on page
trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO
level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger
level is reached, RTS is deasserted. The sending device (e.g., another UART) may
send an additional byte after the trigger level is reached (assuming the sending UART
has another byte to send) because it may not recognize the deassertion of RTS until
it has begun sending the additional byte. RTS is automatically reasserted once the
receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This
reassertion allows the sending device to resume transmission.
The transmitter circuitry checks CTS before sending the next data byte. When CTS is
active, the transmitter sends the next byte. To stop the transmitter from sending the
following byte, CTS must be deasserted before the middle of the last stop bit that is
currently being sent. The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts
because the device automatically controls its own transmitter. Without auto-CTS, the
transmitter sends any data present in the transmit FIFO and a receiver overrun error
may result.
BYTE N
START
STOP
BYTE 0-7
3).
Rev. 04 — 20 June 2003
START
Figure 4
STOP
BYTE N + 1
1
shows RTS functional timing. The receiver FIFO
2
STOP
START
N
BYTE 0-7
Dual UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Section
N+1
SC16C752
Figure 1 “Block
STOP
6.2.1.
002aaa227
002aaa226
START
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