ox16c954 ETC-unknow, ox16c954 Datasheet
ox16c954
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ox16c954 Summary of contents
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... NHANCEMENTS The OX16C954B is an enhanced, backward-compatible revision of the OX16C954 rev A. It uses the newer core as in the OX16C950 rev B. The chief enhancements are as follows – All known errata fixed Full TCR range from 4-16 Enhanced controls for sleep-mode sensitivity, ability to read FCR and Good Data Status 3 ...
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... D ESCRIPTION The OX16C954 is a single chip solution for 4 channel serial add-in cards. Each UART channel in the OX16C954 offers data rates up to 15Mbps and 128-byte deep transmitter and receiver FIFOs. Deep FIFOs reduce CPU overhead and allow utilisation of higher data rates. Each UART channel is software compatible with the widely ...
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... Enhanced Features Register ‘EFR’........................................................................................................................................31 13.2 Special Character Detection ...................................................................................................................................................32 13.3 Automatic In-band Flow Control ............................................................................................................................................32 13.4 Automatic Out-of-band Flow Control ....................................................................................................................................32 14 BAUD RATE GENERATION.............................................................................................................................................................33 14.1 General Operation.....................................................................................................................................................................33 14.2 Clock Prescaler Register ‘CPR’..............................................................................................................................................34 14.3 Times Clock Register ‘TCR’ ....................................................................................................................................................34 14.4 Input Clock Options..................................................................................................................................................................36 Data Sheet Revision 1.0 OX16C954 rev B Page 3 ...
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... Port Index Register ‘PIX’.....................................................................................................................................................42 15.15 Clock Alteration Register ‘CKA’ ........................................................................................................................................42 16 OPERATING CONDITIONS.............................................................................................................................................................. ELECTRICAL CHARACTERISTICS .........................................................................................................................................44 17.1 5V Operation..............................................................................................................................................................................44 17.2 3.3V Operation........................................................................................................................................................................... ELECTRICAL CHARACTERISTICS .........................................................................................................................................46 18.1 5V Operation..............................................................................................................................................................................46 18.2 3.3V Operation...........................................................................................................................................................................47 19 TIMING WAVEFORMS......................................................................................................................................................................48 20 PACKAGE INFORMATION...............................................................................................................................................................50 21 ORDERING INFORMATION.............................................................................................................................................................52 NOTES ......................................................................................................................................................................................................53 CONTACT DETAILS................................................................................................................................................................................54 Data Sheet Revision 1.0 OX16C954 rev B Page 4 ...
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... Device ID 9-bit data frames RS485 buffer enable Infra-red (IrDA) Table 1 OX16C954 performance compared with 16C454, 16C554, 16C654 and 16C750 devices Improvements of the OX16C954 over previous generations of PC UARTs: Deeper FIFOs: The OX16C954 offers 128-byte deep FIFOs for the transmitter and receiver. ...
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... The function of the DTR# pin may be re-assigned to buffer- enable signal for RS485 line driver in half-duplex mode (see ACR[4:3] in section 15.3). Device ID: Four bytes of device ID are available to identify the OX16C954 device to software drivers. Infrared ‘IrDA’ interface: The UART contains an IrDA compliant modulator and demodulator. 9-bit data framing ...
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... Buffer Control NOTE : VDETECT pin is only available on the 80pin TQFP package option Data Sheet Revision 1.0 SERIAL CHANNEL shown ) Control and Status Registers Figure 1: OX16C954 Block Diagram OX16C954 rev B Transmitter SOUTn 128 Byte FIFO SINn Receiver 128 Byte ...
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... SOUT1 19 CS1 INT1 21 RTS1# 22 GND 23 DTR1# 24 CTS1# 25 DSR1 OX16C954-PCC60-B (Rev B) is pin compatible with the previous part OX16C954-PCC60-A (Rev A). Data Sheet Revision 1 ...
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... OX16C954 rev RI2# 57 SIN2 ...
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... This pin can also be used as an alternative external clock pin under software control (replacing XTLI and thus reducing noise/power due to XTLO) for embedded applications. Active-high Hardware Reset. The configuration of OX16C954 after a hardware reset is described in section 7.1. This pin exhibits a small hysteresis to provide noise immunity. This pin must be tied inactive when not in use ...
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... CTS# pin is reasserted. Note: flow control characters are transmitted regardless of the state of the CTS# pin. The state of this pin is reflected in bit 4 of the MSR. It can also be used as a general-purpose input. OX16C954 rev B Page 11 ...
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... Signal for the DMA transfer of receiver data, for Uart 1. Signal for the DMA transfer of receiver data, for Uart 0. There are two modes of DMA signalling described in section 8.1 Signal for DMA transfer of received data. This pin is the wire ”OR-ed” function of the RXRDY# signals of all channels. OX16C954 rev B Page 12 ...
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... TQFP package option. For 5v supply voltage : Vdetect must be tied low. For 3.3v supply voltage : Vdetect must be tied high. NOTE : The PLCC package option does not bond-out this pin, which is internally pulled down to gnd. So the PLCC is suitable for 5v operation only. OX16C954 rev B Page 13 ...
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... PLCC : All VDD pins must be tied to 5 Volts. TQFP : All VDD pins must be tied 3.3v. (Note that the VDETECT pin must be set according to the selected voltage environment). No Connects These pins are not connected to any pads within the device, and can be left open. Table 2: Pin Descriptions OX16C954 rev B Page 14 ...
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... Connect to a suitable line driver Connect to a suitable line receiver Connect to a suitable line receiver Connect to a suitable line receiver Connect to an available processor interrupt line OX16C954 rev B Action when not used Leave unconnected (Internal pull-up) n/a n/a Must be tied low for Motorola mode ...
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... ODE ELECTION The OX16C954 device is a four-channel device backward compatible with the 16C454, 16C554, 16C654 and 16C750 UARTs. Each of the four channels are identical and independent in terms of functionality, with the exception of some shared pins (for example, CLKSEL, FIFOSEL#, CLK and RESET). The remainder of this document therefore discusses the operation of a single channel only ...
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... FCR are ignored). Then arbitrary trigger levels can be defined in RTL, TTL, FCL and FCH registers (see Data Sheet Revision 1.0 OX16C954 rev B section 15). The Additional Status Register (‘ASR’) offers flow control status for the local and remote transmitters. FIFO levels are readable using RFL and TFL registers. ...
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... DSR CTS Temporary data storage register and Indexed control register offset value bits Unused Divisor latch bits [7:0] (Least significant byte) Divisor latch bits [15:8] (Most significant byte) Table 4: Standard 550 Compatible Registers OX16C954 rev B Bit 3 Bit 2 Bit 1 Bit 0 Modem Rx Stat THRE RxRDY ...
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... Char Detect Number of characters in the receiver FIFO Number of characters in the transmitter FIFO Data read/written depends on the value written to the SPR prior to the access of this register (see Table 6: 950 Specific Registers OX16C954 rev B Bit 2 Bit 1 Bit 0 In-band flow control mode Bit 2 Bit 1 ...
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... Reserved Wakeup FCR[6] FCR[5] FCR[4] Unused Force RxRdy Unused inactive Hardwired Port Index ( 0x00, 0x01, 0x02, 0x03 respectively ) Unused CLKSEL Table 7: Indexed Control Register Set OX16C954 rev B Bit 3 Bit 2 Bit 1 Bit 0 Auto Tx Rx DSR Disable Disable Flow Control Enable 3 Bit “fractional” part of ...
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... Write the desired offset to SPR (address 111b). Read the desired value from ICR (address 101b). Write 0x00 offset to SPR to select ACR. Clear bit 6 of ACR bye writing x0xxxxxxb to ICR, thus enabling access to standard registers again. Data Sheet Revision 1.0 OX16C954 rev B Page 21 ...
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... Table 8: Output Signal Reset State Data Sheet Revision 1.0 OX16C954 rev B 7.2 Software Reset An additional feature available in the OX16C954 device is independent software resetting of any of the four serial channels. The software reset is available using the given channels CSR register. The Software reset command has the same effect as a ...
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... FCR[5:4]: THR trigger level Generally in 450, 550, extended 550 and 950 modes these bits are unused (see section 5 for mode definition). In 650 mode they define the transmitter interrupt trigger levels and in 750 mode FCR[5] increase the FIFO size. OX16C954 rev B Page 23 ...
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... The receiver will continue receiving data even if the RHR is full or the receiver has been disabled (see section 15.3) in order to maintain framing synchronisation. The only Data Sheet Revision 1.0 OX16C954 rev B 950 mode: Setting ACR[5]=1 enables 950-mode trigger levels set using the TTL register (see section 15.4), FCR[5:4] are ignored ...
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... The LSR[4] break flag will be set when this data item gets to the top of the RHR and it is cleared following a read of the LSR. LSR[5]: THR empty logic 0 Transmitter FIFO (THR) is not empty. logic 1 Transmitter FIFO (THR) is empty. OX16C954 rev B bit bit of Page 25 ...
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... Disable receiver status and address bit interrupt. logic 1 Enable receiver status and address bit interrupt. Data Sheet Revision 1.0 OX16C954 rev B logic 1 At least one parity error, framing error or break indication in the FIFO. In 450 mode LSR[7] is permanently cleared, otherwise this bit will be set when an erroneous character is transferred from the receiver to the RHR ...
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... FIFO and transmitter shift register are empty and the SOUT line has returned to idle marking state. OX16C954 rev B th data bit) interrupt by Page 27 ...
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... Writing this bit will have no affect on operation. Reading this bit will return the last value written. This bit is only used for test purposes in local loop-back mode (MCR[4] = ‘1’). Data Sheet Revision 1.0 OX16C954 rev B 10.4 Sleep Mode For a channel to go into sleep mode, all of the following conditions must be met: ...
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... DTR (MCR[0]) in internal loop-back mode. MSR[6]: RI This bit is the complement of the RI# input. In internal loop- back mode it is equivalent to the internal OUT1. MSR[7]: DCD This bit is the complement of the DCD# input. In internal loop-back mode it is equivalent to the internal OUT2. rate generator OX16C954 rev B Page 29 ...
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... See section 14 for full details. Data Sheet Revision 1.0 OX16C954 rev B 12.2 Scratch Pad Register ‘SPR’ The scratch pad register does not affect operation of the rest of the UART in any way and can be used for temporary data storage ...
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... XOFF characters when EFR[3:2] = “01” or “10”. EFR[1:0] should not be set to “11” when EFR[3:2] is ‘00’. Data Sheet Revision 1.0 OX16C954 rev B EFR[3:2]: In-band transmit flow control mode When in-band transmit flow control is enabled, an XON/XOFF character is inserted into the data stream whenever the RFL passes the upper trigger level and falls below the lower trigger level respectively ...
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... Data Sheet Revision 1.0 OX16C954 rev B When the 'XON Any' flag (MCR[5]) is set, any received character is accepted as a valid XON condition and the transmitter will be re-enabled. The received data will be transferred to the RHR ...
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... TCR is set to 0x00 (i. 16). Assuming this default configuration, the following table gives the divisors required to be programmed into the DLL and DLM registers in order to obtain various standard baud rates: Data Sheet Revision 1.0 OX16C954 rev B DLM:DLL Baud Rate Divisor Word (bits per second) ...
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... However, each UART of the OX16C954 is designed in a manner to enable it to accept other multiplications of the bit rate clock. It can use values from 4x to 16x clock as programmed in the TCR as long as the clock (oscillator) frequency error, stability and jitter are within reasonable parameters ...
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... OX16C954 rev B Max. Baud rate with CPR = 1, TCR = 4 460,800 1,843,200 3,686,400 4,608,000 8,000,000 ...
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... MDM register, see section 15.10). 14.7 Crystal Oscillator Circuit The OX16C954 may be clocked by a crystal connected to XTLI and XTLO or directly from a clock source connected to the XTLI pin (or CLKSEL if selected by software). The circuit required to use the on-chip oscillator is shown in Figure 3 ...
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... This can be used to determine whether a level 5 interrupt was caused by receiving a special character rather than an XOFF. The flag is cleared following the read of the ASR. Data Sheet Revision 1.0 OX16C954 rev B ASR[5]: FIFOSEL This bit reflects the unlatched state of the FIFOSEL pin. ASR[6]: FIFO size logic 0 FIFOs are 16 deep if FCR[ ...
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... When the transmitter is empty the DTR# would go inactive once the SOUT line returns to it’s idle marking state. Data Sheet Revision 1.0 OX16C954 rev B ACR[5]: 950 mode trigger levels enable logic 0 Interrupts and flow control trigger levels are as described in FCR register and are compatible with 16C650/16C750 modes ...
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... ID registers may be read using offset values 0x08 to 0x0B of the Indexed Control Register. Registers ID1, ID2 and ID3 identify the device as an OX16C954 and return 0x16, 0xC9 and 0x54 respectively. The REV register resides at offset 0x0B of ICR and identifies the revision of 950 core ...
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... The transmitter is in isochronous 1x clock mode. Data Sheet Revision 1.0 OX16C954 rev B 15.9 Nine-bit Mode Register ‘NMR’ The NMR register is located at offset 0x0D of the ICR The UART offers 9-bit data framing for industrial multi-drop applications. The 9-bit mode is enabled by setting bit 0 of the Nine-bit Mode Register (NMR) ...
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... Delta DSR is disabled. It can not generate an interrupt or wake up the UART. Data Sheet Revision 1.0 OX16C954 rev B MDM[2]: Disable Trailing edge RI logic 0 Trailing edge RI is enabled. It can generate a level 4 interrupt when enabled by IER[3]. Trailing edge RI can wake up the UART when it is asleep under auto-sleep operation ...
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... UART index. This returns depending on which UART is being accessed. Data Sheet Revision 1.0 OX16C954 rev B 15.15 Clock Alteration Register ‘CKA’ The CKA register is located at offset 0x13 of the ICR. This register adds additional clock control mainly for isochronous and embedded applications ...
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... VDETECT held high gives CMOS type I/Os that scale better with Voltage, so should be used if a voltage between these ranges is used, but the thresholds are not guaranteed. Data Sheet Revision 1.0 Min. -0.3 -0.3 -40 Table 20: Absolute Maximum Ratings Min 4.75 0 Min 3.0 0 OX16C954 rev B Max. Units 7 0 +/- 10 mA 125 C Max Units 5 ...
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... Note2 current 1.8432 MHz 7.372 MHz 50.00 MHz 1.8432 MHz 7.372 MHz 50.00 MHz CK Table 22: DC Electrical Characteristics (5v) OX16C954 rev B Min. Max. Units 4.75 5.25 V 2.0 V 2.4 0.8 V 0.6 5.0 pF 10 – 0. 2.4 V 0.05 V 0.4 ...
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... Note2 current 1.8432 MHz 7.372 MHz 50.00 MHz 1.8432 MHz 7.372 MHz 50.00 MHz CK OX16C954 rev B Min. Max. Units 3.00 3. 1.6 0 1.2 5.0 pF 10 – 0. 2.4 V 0.05 V 0.4 ...
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... Delay to start of next read/write cycle (write cycle) dw2 t Write data set-up time to DS# rising sd t Write data valid after DS# rising hdw Table 25: Data bus timing for Motorola mode: Data Sheet Revision 1.0 Table 24: Data bus timing for Intel mode OX16C954 rev B Min Max Units ...
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... Delay to start of next read/write cycle (write cycle) dw2 t Write data set-up time to DS# rising sd t Write data valid after DS# rising hdw Table 27: Data bus timing for Motorola mode: Data Sheet Revision 1.0 Table 26: Data bus timing for Intel mode OX16C954 rev B Min Max Units ...
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... CS2#, CS3# IOW# DB[7:0] Data Sheet Revision 1.0 Address Valid acc Data Valid Figure 4: Intel Mode Read Cycle Timing Address Valid Data Valid Figure 5: Intel Mode Write Cycle Timing OX16C954 rev ...
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... Data Sheet Revision 1.0 Address Valid srwr t acc Data Valid Figure 6: Motorola Mode Read Cycle Timing Address Valid srww t sd Data Valid Figure 7: Motorola Mode Write Cycle Timing OX16C954 rev hrwr t dr1 t dr2 t hdr hrw w t dw1 ...
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... OXFORD SEMICONDUCTOR LTD ACKAGE NFORMATION OX16C954-PCC60-B Data Sheet Revision 1.0 Figure 8: 68 Pin Plastic Leaded Chip Carrier OX16C954 rev B Page 50 ...
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... OXFORD SEMICONDUCTOR LTD. Data Sheet Revision 1.0 Figure 9: 68 Pin Plastic Leaded Chip Carrier OX16C954 rev B Page 51 ...
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... OXFORD SEMICONDUCTOR LTD RDERING NFORMATION OX16C954-PCC60-B Revision Operating Conditions -Commercial Package Type - OX16C954-TQC60-B Revision Operating Conditions -Commercial Package Type – 80TQFP Data Sheet Revision 1.0 OX16C954 rev B Page 52 ...
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... OXFORD SEMICONDUCTOR LTD. N OTES Data Sheet Revision 1.0 This page has intentionally been left blank. OX16C954 rev B Page 53 ...
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C D ONTACT ETAILS Oxford Semiconductor Ltd. 25 Milton Park Abingdon Oxfordshire OX14 4SH United Kingdom Telephone: +44 (0)1235 824900 Fax: +44 (0)1235 821141 Sales e-mail: sales@oxsemi.com Web site: http://www.oxsemi.com ©Copyright Oxford Semiconductor Ltd 2001 Oxford Semiconductor Ltd believes the ...