ox16c954 ETC-unknow, ox16c954 Datasheet - Page 22

• Manufacturer Part Number: ox16c954
• Description: High Performance Quad Uart With 128-byte Fifos Intel / Motorola Bus Interface
• Manufacturer: ETC-unknow

7
7.1
After a hardware reset, all writable registers are reset to
0x00, with the following exceptions:
1. DLL which is reset to 0x01.
2. MCR[7] is reset to the complement of the CLKSEL
3. CPR is reset to 0x20.
The state of read-only registers following a hardware reset
is as follows:
RHR[7:0]: Indeterminate
RFL[6:0]: 0000000
TFL[6:0]: 0000000
LSR[7:0]: 0x60 signifying that both the transmitter and the
MSR[3:0]: 0000
MSR[7:4]: Dependent on modem input lines DCD, RI,
ISR[7:0]: 0x01, i.e. no interrupts are pending
ASR[7:0]: 1xx00000
RFC[7:0]: 00000000
GDS[7:0]: 00000001
DMS[7:0]: 00000010
CKA[7:0]: 00000000
The reset state of output signals are tabulated below:
Data Sheet Revision 1.0
OXFORD SEMICONDUCTOR LTD.
RXRDY#
TXRDY#
SOUTn
input pin value (see section 11.1 ).
RTSn#
DTRn#
Signal
INTn /
IRQ#
R
Hardware Reset
ESET
transmitter FIFO are empty
DSR and CTS respectively
Table 8: Output Signal Reset State
C
Inactive low when INTSEL# pin is held high
2
ONFIGURATION
Active low (THR is able to receive data).
2
2
2
2
2
2
2
otherwise high-impedance
Inactive High
Inactive High
Inactive High
Inactive High
Reset state
7.2
An additional feature available in the OX16C954 device is
independent software resetting of any of the four serial
channels. The software reset is available using the given
channels CSR register.
The Software reset command has the same effect as a
hardware reset except it only resets the channel whose
CSR register is written, the state of all other channels
remains unchanged. Also it does not reset the clock source
selections (i.e. CKS register and CKA register). To reset a
channel, write 0x00 to the Channel Software Reset register
‘CSR’.
Software Reset
OX16C954 rev B
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