ox16c954 ETC-unknow, ox16c954 Datasheet - Page 37

• Manufacturer Part Number: ox16c954
• Description: High Performance Quad Uart With 128-byte Fifos Intel / Motorola Bus Interface
• Manufacturer: ETC-unknow

15 A
15.1 Additional Status Register ‘ASR’
ASR[0]: Transmitter disabled
logic 0
logic 1
This bit is cleared after a hardware reset or channel
software reset. The software driver may write a 0 to this bit
to re-enable the transmitter if it was disabled by in-band
flow control. Writing a 1 to this bit has no effect.
ASR[1]: Remote transmitter disabled
logic 0
logic 1
This bit is cleared after a hardware reset or channel
software reset. The software driver may write a 0 to this bit
to re-enable the remote transmitter (an XON is
transmitted). Note: writing a 1 to this bit has no effect.
Note: The remaining bits (ASR[7:2]) are read-only.
ASR[2]: RTS
This is the complement of the actual state of the RTS# pin
when the device is not in loopback mode. The driver
software can determine if the remote transmitter is disabled
by RTS# out-of-band flow control by reading this bit. In
loopback mode this bit reflects the flow control status rather
than the pin’s actual state.
ASR[3]: DTR
This is the complement of the actual state of the DTR# pin
when the device is not in loopback mode. The driver
software can determine if the remote transmitter is disabled
by DTR# out-of-band flow control by reading this bit. In
loopback mode this bit reflects the flow control status rather
than the pin’s actual state.
ASR[4]: Special character detected
logic 0
logic 1
This can be used to determine whether a level 5 interrupt
was caused by receiving a special character rather than an
XOFF. The flag is cleared following the read of the ASR.
Data Sheet Revision 1.0
OXFORD SEMICONDUCTOR LTD.
DDITIONAL
The transmitter is not disabled by in-band flow
control.
The receiver has detected an XOFF, and has
disabled the transmitter.
The remote transmitter is not disabled by in-
band flow control.
The transmitter has sent an XOFF character, to
disable the remote transmitter (cleared when
subsequent XON is sent).
No special character has been detected.
A special character has been received and is
stored in the RHR.
F
EATURES
ASR[5]: FIFOSEL
This bit reflects the unlatched state of the FIFOSEL pin.
ASR[6]: FIFO size
logic 0
logic 1
Note: If FCR[0] = 0, the FIFOs are 1 deep.
ASR[7]: Transmitter Idle
logic 0
logic 1
This bit reflects the state of the internal transmitter. It is set
when both the transmitter FIFO and shift register are
empty.
15.2 FIFO Fill levels ‘TFL & RFL’
The number of characters stored in the THR and RHR can
be determined by reading the TFL and RFL registers
respectively. As the UART clock is asynchronous with
respect to the processor, it is possible for the levels to
change during a read of these FIFO levels. It is therefore
recommended that the levels are read twice and compared
to check that the values obtained are valid. The values
should be interpreted as follows:
1.
2.
15.3 Additional Control Register ‘ACR’
The ACR register is located at offset 0x00 of the ICR
ACR[0]: Receiver disable
logic 0
logic 1
Changes to this bit will only be recognised following the
completion of any data reception pending.
The number of characters in the THR is no greater
than the value read back from TFL.
The number of characters in the RHR is no less than
the value read back from RFL.
FIFOs are 16 deep if FCR[0] = 1.
FIFOs are 128 deep if FCR[0] = 1.
Transmitter is transmitting.
Transmitter is idle.
The receiver is enabled, receiving data and
storing it in the RHR.
The receiver is disabled. The receiver
continues to operate as normal to maintain the
framing synchronisation with the receive data
stream but received data is not stored into the
RHR. In-band flow control characters continue
to be detected and acted upon. Special
characters will not be detected.
OX16C954 rev B
Page 37