ox16c954 ETC-unknow, ox16c954 Datasheet - Page 18

• Manufacturer Part Number: ox16c954
• Description: High Performance Quad Uart With 128-byte Fifos Intel / Motorola Bus Interface
• Manufacturer: ETC-unknow

3.
6
The UART is accessed through an 8-byte block of I/O space (or through memory space). Since there are more than 8 registers,
the mapping is also dependent on the state of the Line Control Register ‘LCR’ and Additional Control Register ‘ACR’:
1.
2.
4.
Data Sheet Revision 1.0
OXFORD SEMICONDUCTOR LTD.
Register
650 mode
750 mode
950 mode
9-bit data
9-bit data
650/950
550/750
550/750
650/950
Name
MCR
Normal
Normal
LSR
MSR
RHR
IER
THR
Mode
Mode
FCR
LCR
Mode
Mode
mode
SPR
mode
ISR
LCR[7]=1 enables the divider latch registers DLL and DLM.
LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables
access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection.
ACR[7]=1 enables access to the 950 specific registers.
ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 20.
DLM
DLL
R
EGISTER DESCRIPTION TABLES
Additional Standard Registers – These registers require divisor latch access bit (LCR[7]) to be set to 1.
1,2
3,5
3
3,4
4
1
3
3
1
3
Address
000
000
001
010
010
011
100
101
110
111
000
001
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
R
R
prescale
interrupt
Divisor
access
Bit 7
mask
Baud
Error
DCD
latch
Data
CTS
RHR Trigger
RHR Trigger
Table 4: Standard 550 Compatible Registers
enabled
Unused
Unused
FIFOs
Level
Level
Tx Empty
interrupt
Bit 6
break
mode
mask
RTS
IrDA
Tx
RI
Unused
XON-Any
Alternate
Special
Control
Divisor latch bits [15:8] (Most significant byte)
Detect
CTS &
Empty
Divisor latch bits [7:0] (Least significant byte)
Bit 5
Force
Char.
mode
parity
sleep
FIFO
(Enhanced mode)
Flow
THR
DSR
Size
RTS
Interrupt priority
Indexed control register offset value bits
THR Trigger
Temporary data storage register and
Level
Data to be transmitted
Unused
Internal
Unused
Enable
Bit 4
Sleep
mode
Break
Odd /
parity
Loop
Back
even
CTS
Rx
Data received
(interrupt
Framing
interrupt
Modem
enable)
Mode /
Trigger
Enable
enable
Bit 3
OUT2
Parity
mask
Delta
DMA
Error
DCD
Tx
Interrupt priority
(All modes)
interrupt
Number
RI edge
Trailing
Rx Stat
data bit
of stop
OUT1
Bit 2
Parity
9
mask
Flush
used)
Error
THR
(not
bits
th
Rx
interrupt
Overrun
OX16C954 rev B
THRE
Bit 1
Flush
mask
Delta
RHR
Error
DSR
RTS
Data length
Interrupt
interrupt
pending
RxRDY
RxRDY
Enable
data bit
Bit 0
mask
FIFO
Delta
9
DTR
Page 18
CTS
th
Tx