hsp50415 Intersil Corporation, hsp50415 Datasheet
hsp50415
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hsp50415 Summary of contents
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... The WPM combines shaping and interpolation filters, a complex modulator, timing and carrier NCOs and dual DACs into a single package. The HSP50415 supports vector modulation, accepting up to 16-bit In phase (I) and Quadrature (Q) samples to generate virtually any quadrature modulation format. A constellation mapper and 24 Symbol span interpolation shaping filter is provided for the input baseband signals ...
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... DIGITAL PLL REFCLK 2 HSP50415 HSP50415 (100 LD MQFP) TOP VIEW 100 HSP50415 CARRIER COS ...
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Functional Block Diagram μP RESET INTERFACE ADDR<2:0> CDATA<7:0> INTREQ x2 INTERPOLATION DIN<15:0> CONST. I MAP ISTRB FIR DATACLK BYPASS DATA TXEN INTERFACE/ FEMPT FIFO FOVRFL FFULL Q FIR BYPASS BYPASS 2XSYMCLK X 2 PHASE ...
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... Current Outputs of the Device. Full scale output current is achieved when all input bits are set to binary 1. QOUTA IOUTB, O Complementary Current Outputs of the Device. Full scale output current is achieved on the complementary outputs QOUTB when all input bits are set to binary 0. 4 HSP50415 DESCRIPTION . H FN4559.6 April 23, 2007 ...
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... V SET FSADJ System CLK Generation The HSP50415 receives I and Q input data serially at twice the input symbol rate. The data is converted to a parallel quadrature data stream at the symbol rate by the Front End Data Input Block. This data stream is upsampled to the final output sample rate of the device (FSout) ...
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... SYSCLK/2 2 DIN<15:0> DATA I CONST. INTERFACE MAP Q FIFO DATACLK 2XSYMCLK X 2 Internal IC signal names are shown in lowercase. TABLE 1. HSP50415 FILTER CONFIGURATIONS AND RESULTING SYMBOL NCO RATES BYPASS FIR FILTER FIR INTERPOLATION 0 x2 (Note (Note Not applicable 1 Not applicable NOTE: An optional decimate by two mode allows the device to achieve interpolation by a factor of two in the Shaping FIR ...
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... This resulting rate is affected by rate adjustments (interpolation) in the previous filter blocks. Digital Phase Lock Loop The HSP50415 contains a Digital Phase Lock Loop (DPLL) that performs symbol tracking to an external symbol clock (REFCLK). The DPLL consists of a programmable phase/frequency error detector followed by a loop filter and lock detector stage ...
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... The lock integrator resets to a full-scale negative value. The sign bit of the lock integrator is output as the LOCKDET status flag. The values added or subtracted to the lock integrator are user selectable as follows in Table 2. 8 HSP50415 carryOut 14-BIT SYMBOL NCO COUNTER 8 upper bits of phaseAccum R FIGURE 2 ...
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... Front-End Data Input Block The HSP50415 accepts input data in a parallel bit fashion with I and Q samples input serially as shown in Figure 5. The signal pins on the device that input data to the front-end are the DIN<15:0> bus, the ISTRB and TXEN control pins and the DATACLK pin ...
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... For bit widths less than 4-bits the data in the RAM may simply be zero’s for the unused bit positions and the unused addresses since the HSP50415 will discard the unused bits. For example, if the user programs the number of bits and the upper bits of the DIN<15:0> ...
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... The output of this filter is rounded to 16- bits. The output is checked for saturation and limited if necessary. The data exits the halfband filters as a parallel I<15:0> and Q<15:0> data stream at the interpolated sample rate. Figure 8 shows the frequency response of the Half-Band filter. 11 HSP50415 100 ...
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... RESPONSE FOR L = 16; FOUT = 4096 0 -10 -20 -30 INTERPOLATION -40 FILTER -50 RESPONSE -60 -70 -80 -90 -100 -110 -120 0 512 1024 SAMPLE TIMES FIGURE 13. RESPONSE FOR FOUT = 4096 12 HSP50415 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 3072 3584 4096 FIGURE 10. 0 -10 -20 -30 -40 -50 -60 ...
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... The carrier NCO has a 32-bit programmable frequency increment value which is programmed as follows: carrierPhinc = (carrierFrequency / FSout) * 2^32 The frequency may be positive or negative with a range from -50 to +50MHz (for FSout of 100MHz). The phase adder and accumulator are also 32-bits wide. 13 HSP50415 (Continued) -100 -110 -120 1536 2048 ...
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... Outputs The 5 MSBs for each DAC on the HSP50415 drive a thermometer decoder, which is a digital decoder that has a 5-bit binary coded input word with 2 where the number of output bits that are active correlate directly to the input binary word. The HSP50415 uses a thermometer decoder to significantly minimize the output glitch energy for each DAC ...
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... Microprocessor Interface The HSP50415 is highly configurable with 16 writable/readable control registers and four addresses reserved for generating internal control signals. The microprocessor interface (uPI parallel bus type with the following device pins being used for I/O: CDATA< ...
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... HSP50415 ADDR<2: 0> Writing and reading back the internal RAMs require a different sequence of writes and reads. Each RAM on the device is accessible through the uPI, with the FIFO only having readback capability ...
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... HSP50415 MasterReg<23:0>. Which section of the memory buffer gets the data is dependent on the memory word select counter shown in column 7 of Table 9. A memUpdate strobe increments the word select counter as well as updating the memBuffer. When the word select counter is equal to 2 and a memUpdate strobe occurs, memBuf< ...
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... Read byte # of MemWord<x> (x=memAddr<7:0>, byte # =byteCount<3:0> Read byte # of MemWord<x> (x=memAddr<7:0>, byte # =byteCount<3:0>) 18 HSP50415 will reset the byte counter write to address 7 will increment the byte counter so the WR clock must be pulsed during the memory reads in order to increment the byte counter. Table 11 defines the sequence of writes/reads necessary to read back the I channel coefficient memory data at memory address 0x12 ...
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... BIT NO. 31:16 Symbol NCO Counter MaxCount<15:0> 15 Symbol NCO Counter Mode Enable 14 Fast DAC delay 13 Bypass Final Interpolation Filter 19 HSP50415 TABLE 13. HSP50415 REGISTER SUMMARY REGISTER NAME TABLE 14. MEMORY WRITE/READ CONTROL ADDRESS = 00 H DESCRIPTION TABLE 15. DEVICE CONFIGURATION CONTROL ADDRESS = 01 H DESCRIPTION RESET VALUE 0x00 ...
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... FIFO TXEN Zero Data. (Function: If FIFO Reads are gated with TXEN Pin then force data out of FIFO block to 0x0000 if TXEN is inactive.) 18 FIFO TXEN Enable Gated Write 0 = TXEN Pin gates writing to FIFO 1 = FIFO writes not gated by TXEN 20 HSP50415 ADDRESS = 01 H DESCRIPTION B12 -1 TABLE 16. FIFO AND I/O CONTROL ...
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... I Subtract DC Offset 1:0 I Programmable Round Rounding Round to 14-bits at output Round to 12-bits at output Round in both positions B 21 HSP50415 TABLE 16. FIFO AND I/O CONTROL (Continued) ADDRESS = 02 H DESCRIPTION TABLE 17. I CHANNEL CALIBRATION ADDRESS = 03 H DESCRIPTION RESET STATE ...
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... Bits 27:24 = lag[3:0] Bits 23:20 = frq[3:0] Bits 19:16 = lead[3:0] 15:1 Loop Filter Shifts: Bits 15:11 = lag[4:0] Bits 10:6 = frq[4:0] Bits 5:1 = lead[4:0] 0 Zero Loop Filter Accumulator 22 HSP50415 TABLE 18. Q CHANNEL CALIBRATION ADDRESS = 04 H DESCRIPTION TABLE 19. GAIN AND PHASE ERROR CONTROL ADDRESS = 05 H DESCRIPTION TABLE 20. DIGITAL LOOP FILTER CONTROL ADDRESS = 06 ...
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... BIT NO. 7 Not Used 6 FIFO Full 5 FIFO Empty 4 FIFO Overflow 3 FIFO Underflow 2 Digital PLL Lock Detect 1 Analog PLL Lock Detect 0 Reset Done 23 HSP50415 TABLE 21. LOCK DETECT CONTROL ADDRESS = 07 H DESCRIPTION TABLE 22. INTERRUPT STATUS ADDRESS = 08 H DESCRIPTION RESET STATE 0 000 08000 ...
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... Writing to control word 0x0E generates an internal FIFOReset strobe that resets the FIFO address pointers and flags. BIT NO. NA Writing to control word 0x0F generates an internal memBuf update strobe that downloads the appropriate MasterReg byte to the memory Buffer. 24 HSP50415 TABLE 23. INTERRUPT ENABLE ADDRESS = 09 H DESCRIPTION TABLE 24. CARRIER FREQUENCY ADDRESS = 0A ...
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... ADDRESS = 12 H DESCRIPTION Evaluation Kit The HSP50415EVAL1 is an evaluation kit for the HSP50415 wideband programmable modulator. The kit consists of an evaluation Circuit Card Assembly complete with the HSP50415 device and additional circuitry to provide for control via a computer parallel port. Windows based ...
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... DA CDATA<7:0> Output Delay CHARACTERISTICS: DIGITAL I/Q DATA INPUT DATACLK Frequency, F DCLK DATACLK High, T DCH 26 HSP50415 Thermal Information Thermal Resistance (Typical, Note 2) + 0.5V) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . DD Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to +150°C Vapor Phase Soldering, 1 Minute MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C = -40° ...
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... JA 3. Gain Error measured as the error in the ratio between the full scale output current and the current through R ratio should be 32. 4. See ‘Definition of DAC Specifications’ section. 27 HSP50415 = -40°C to +85°C, Unless Otherwise Specified (Continued) A TEST CONDITION DIN<15:0>, TXEN, ISTRB to DATACLK, (Note 1) DIN< ...
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... CLK AND RELATIVE RESET TIMING WR CDATA<7:0>, ADDR<2:0>, AND FIGURE 24. TIMING RELATIVE TO WR, LOADING SEQUENCE AND ADDR. ADDR<2:0> VALID CDATA<7:0> RD AND CE FIGURE 26. TIMING RELATIVE TO WR, READING SEQUENCE 28 HSP50415 // t RTH RPW CLK CLK DATA VALID t t DCL DCH DATACLK t ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 29 HSP50415 Q100.14x20 100 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYMBOL ...