hsp50415 Intersil Corporation, hsp50415 Datasheet - Page 21

• Manufacturer Part Number: hsp50415
• Description: Wideband Programmable Modulator Wpm
• Manufacturer: Intersil Corporation

BIT NO.
BIT NO.
31:24
23:14
13:4
1:0
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
0
3
2
FIFO Threshold Upper Limit<7:0>
I Scale Factor<9:0>
I DC Offset <9:0>
I Negate Scale Factor
I Subtract DC Offset
I Programmable Round
00
01
10
11
FIFO TXEN Gated Read
0 = FIFO reads not gated by TXEN (reads begin after 2 FIFO locations written)
1 = TXEN Pin gates read from FIFO
FIFO Underflow/Empty Pin Function
0 = Output FIFO underflow status on Pin FEMPT
1 = Output FIFO empty status on Pin FEMPT
2XSYMCLK polarity
2XSYMCLK Three-State enable
0 = off
1 = enable output
FFULL, FIFO Full Output Enable
FOVRFL, FIFO Overflow Output Enable
FEMPT, FIFO Under/Empty Output Enable
LOCKDET Output Enable
SYSCLK/2 Output Enable
INTREQ Pin Output Enable
IOUT<13:0> Output Enable
QOUT<13:0> Output Enable
TXEN Polarity
0 = Active High
1 = Active Low
ISTRB Polarity.
0 = Active High (DIN<15:0> contains Isample when ISTRB is high)
1 = Active Low (DIN<15:0> contains Isample when ISTRB is low)
SYSCLK/2 polarity.
0 = IOUT<13:0>/QOUT<15:0> data out on falling edge
1 = IOUT<13:0>/QOUT<15:0> data out on rising edge
FIFO Gated Read No Address Reset
IDAC Power Enable
QDAC Power Enable
B
B
B
B
= Round in both positions
= No Rounding
= Round to 14-bits at output
= Round to 12-bits at output
21
TABLE 16. FIFO AND I/O CONTROL (Continued)
TABLE 17. I CHANNEL CALIBRATION
DESCRIPTION
DESCRIPTION
ADDRESS = 02
ADDRESS = 03
HSP50415
H
H
RESET STATE
RESET STATE
000
000
FF
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
April 23, 2007
H
B
H
H
FN4559.6