ak4126 AKM Semiconductor, Inc., ak4126 Datasheet
ak4126
Available stocks
Related parts for ak4126
ak4126 Summary of contents
Page 1
... AK4126 is a 6ch digital sample rate converter (SRC). The input sample rate ranges from 8kHz to 192kHz. The output sample rate is from 8kHz to 192kHz. By using the AK4126, the system can take very simple configuration because the AK4126 has an internal PLL and does not need any master clock Then the AK4126 is suitable for the application interfacing to different sample rates like multi-channel high-end Car Audio, DVD recorder, etc ...
Page 2
... Maximum Sampling Frequency Maximum BICK Frequency Bypass Mode Master Mode De-emphasis Variable Soft Mute Cycle Group Delay Package MS0544-E-00 DVDD DVSS ODIF1 ODIF0 DEM SRC Figure 1. AK4126 Block Diagram AK4126 6ch 192kHz 64fs No No Yes Yes typ. 57/fs 64LQFP(12mm x 12mm [AK4126] OBIT1 ...
Page 3
... MS0544-E-00 AK4126 IBCLK OBCLK ILRCK OLRCK SRC SDTO1-3 SDTI1-3 3 SRC AK4126 IBCLK OBCLK ILRCK OLRCK SRC SDTO1-3 SDTI1-3 3 SRC - 3 - [AK4126] ASIC BCLK LRCK 3 SDTI fs = 192kHz fs = 176.4kHz fs = 96kHz fs = 88.2kHz fs = 48kHz fs = 44.1kHz MOST or ASIC BCLK LRCK 3 SDTI fs = 96kHz fs = 88.2kHz fs = 48kHz fs = 44.1kHz 2006/09 ...
Page 4
... ASAHI KASEI Ordering Guide −40 ∼ +85°C AK4126VQ AKD4126 Evaluation Board for AK4126 Pin Layout NC 1 TEST0 2 ILRCK 3 IBICK 4 DVDD 5 DVSS 6 TST0 7 SDTI1 8 SDTI2 9 SDTI3 10 IDIF0 11 IDIF1 12 IDIF2 13 TST1 14 TST2 MS0544-E-00 64LQFP (0.5mm pitch) Top View - 4 - [AK4126 TEST4 46 OLRCK ...
Page 5
... Dither ON, “L” : Dither OFF Power-Down Mode Pin 24 PDN I “H”: Power up, “L”: Power down reset and initializes the control register. The AK4126 should be reset once by bringing PDN pin = “L” upon power-up. 25 SMT0 I Soft Mute Timer Select #0 Pin 26 ...
Page 6
... This pin must be connected to DVSS. Analog Power Supply Pin, 3.0 ∼ 3.6V 60 AVDD - 61 FILT O PLL Loop Filter Pin 62 AVSS - Analog Ground Pin TEST Pin 63 TST11 O This pin must be open. Note: All input pins should not be left floating. MS0544-E-00 PIN / FUNCTION Function - 6 - [AK4126] 2006/09 ...
Page 7
... This pin must be connected to DVDD. These pins must be open. ABSOLUTE MAXIMUM RATINGS Symbol min −0.3 AVDD −0.3 DVDD IIN - −0.3 (Note 3) VIND −40 Ta −65 Tstg Symbol min AVDD 3.0 DVDD 3.0 AVDD - DVDD -0 [AK4126] max Units 4.6 V 4.6 V ±10 mA DVDD+0.3 V °C 85 °C 150 typ max Units 3.3 3.6 V 3.3 3 +0.3 V ...
Page 8
... Worst Case (FSO/FSI = 48kHz/32kHz) Dynamic Range (Input = 1kHz, −60dBFS, A-weighted, Note 6) FSO/FSI = 44.1kHz/48kHz Ratio between Input and Output Sample Rate Note 6. Measured by Audio Precision System Two Cascade. MS0544-E-00 SRC CHARACTERISTICS Symbol FSI FSO FSO/FSI - 8 - [AK4126] min typ max Units 24 Bits 8 192 kHz 8 192 kHz − ...
Page 9
... SA 121.4 SA 115.3 SA 116.9 SA 114.6 SA 100.2 SA 103.3 SA 102.0 SA 103.6 SA 104.0 SA 103.3 SA 73.2 (Note [AK4126] typ max Units 0.4583FSI kHz 0.4167FSI kHz 0.3195FSI kHz 0.2852FSI kHz 0.2182FSI kHz 0.2177FSI kHz 0.1948FSI kHz 0.1458FSI kHz 0.1302FSI kHz 0.0917FSI kHz 0.0826FSI kHz 0.0583FSI kHz ...
Page 10
... This value is measured after the internal SRAM is initialized by inputting “0” data to SDTI1, SDTI2, and SDTI3 during (ILRCK x 100) cycles. MS0544-E-00 DC CHARACTERISTICS Symbol min VIH 70%DVDD VIL - VOH DVDD−0.4 VOL - Iin - (Note [AK4126] typ max Units - - V - 30%DVDD 0.4 V ±10 µA ...
Page 11
... OLRCK to SDTO (MSB) (Except I OBICK “↓” to SDTO Reset Timing PDN Pulse Width Note 9. BICK rising edge must not occur at the same time as LRCK edge. Note 10. The AK4126 can be reset by bringing the PDN pin = “L”. MS0544-E-00 SWITCHING CHARACTERISTICS =20pF) L ...
Page 12
... Note: BICK shows IBICK and OBICK. LRCK shows ILRCK and OLRCK. SDTI shows SDTI1, SDTI2 and SDTI2. SDTO shows SDTO1, SDTO2 and SDTO3. PDN MS0544-E-00 1/fs tBCK tBCKL Clock Timing tLRB tBSD tSDS tSDH Audio Interface Timing tPD Power Down & Reset Timing - 12 - [AK4126] VIH VIL VIH VIL VIH VIL VIH VIL 50%DVDD VIH VIL VIL 2006/09 ...
Page 13
... L L 32fsi (Note 13 (Note 12 ∼ 192kHz H H (Note 12) Table 2. PLL Setting (Input PORT [AK4126] IBICK Frequency ≥ 32fsi ≥ 40fsi ≥ 48fsi ≥ 48fsi or 32fsi ≥ 48fsi SMUTE (Note 14) Manual IDIF2-0 (Note 12) Semi-Auto Reserved Manual 64fsi ...
Page 14
... Lch Data Figure 4. Mode 2 Timing (24bit MSB Don't Care 23 22 Lch Data 2 Figure 5. Mode 3 Timing (24bit [AK4126 Rch Data ...
Page 15
... Figure 7. LSB Timing - 15 - [AK4126 Rch Data 2 S LSB justified 64fso ...
Page 16
... Note: SDTO shows SDTO1, SDTO2 and SDTO3. 4-channel Mode The AK4126 has 4-channel mode to reduce power supply current when using four channels in six channels. When PM pin is set to “H”, four channels (SDTI1 SDTO1 and SDTI2 SDTO3) are powered-down (SDTO3 outputs “L”.). ...
Page 17
... Figure 10. Soft Mute Function (Manual Mode) MS0544-E-00 Period fso=48kHz fso=96kHz 1024/fso 21.3ms 2048/fso 42.7ms 4096/fso 85.3ms 8192/fso 170.7ms Table 6. Soft Mute Cycle Setting (1) ( [AK4126] fso=192kHz 10.7ms 5.3ms 21.3ms 10.7ms 42.7ms 21.3ms 85.3ms 42.7ms (2) 2006/09 ...
Page 18
... The output data is attenuated by −∞ during the soft mute cycle (See Table 6) Figure 11. Soft Mute Function (Semi-Auto Mode) Dither The AK4126 includes the dither circuit. The dither circuit adds the dither to the LSB of all the output data set with the OBIT1-0 pins by DITHER pin = “H”. De-emphasis Filter The AK4126 includes a digital de-emphasis filter (tc = 50/15µ ...
Page 19
... System Reset Bringing the PDN pin = “L” sets the AK4126 power-down mode and initializes the digital filter. The AK4126 should be reset once by bringing PDN pin = “L” upon power-up. When PDN pin = “L”, the SDTO output is “L”. The SDTO valid time is 100ms. Until then, the SDTO outputs “ ...
Page 20
... ASAHI KASEI Internal Reset Function for Clock Change The change of the clock supplied to the AK4126 is shown in Figure 14. SDTO shows SDTO1, SDTO2 and SDTO3. External clocks (Input port or Output port) PDN pin (Internal state) Normal operation SDTO Normal data SMUTE (Note2, recommended) 0dB Att ...
Page 21
... Table 8. PLL Loop Filter (ILRCK Mode) ILRCK R [Ω] 8k ∼ 192kHz 470 ± Compatible [AK4126] C2 [nF] C1 [µF] 0.68 ± 30% 0.68 ± 30% 1.0 ± 30% 2.2 ± 30% 0.68 ± 30% 0.68 ± 30% 1.0 ± 30% 2.2 ± 30% 0.68 ± 30% 0.68 ± 30% C1 [µF] C2 [nF] 0.22 ± ...
Page 22
... Top View Figure 16. Typical Connection Diagram - 22 - [AK4126 TEST4 47 fso OLRCK 46 64fso OBICK 45 C1 DVDD 44 DVSS 43 DSP2 TST6 42 SDTO1 41 SDTO2 40 SDTO3 39 ODIF0 38 ODIF1 37 TEST3 36 TEST2 ...
Page 23
... Jitter Tolerance Figure 17 shows the jitter tolerance to ILRCK and IBICK for AK4126. The jitter frequency and the jitter amplitude shown in Figure 17 define the jitter quantity. When the jitter amplitude is 0.01Uipp or less, the AK4126 operate normally regardless of the jitter frequency. ...
Page 24
... When the ILRCK is generated by an external PLL, it may take a time to settle after changing the input sampling frequency because the response of an external PLL to the frequency change is slow. AK4126 operates normally up to 23%/sec speed and the output data becomes incorrect at the speed of the frequency change over 23%/sec. ...
Page 25
... ASAHI KASEI 64pin LQFP(Unit:mm) 12.0±0.3 10 0.21±0.05 Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0544-E-00 PACKAGE 1.70max 1. 0.10 M 1.0 0° ~10° 0.45±0.2 0.10 Epoxy Cu Solder (Pb free) plate - 25 - [AK4126] 0.10±0.10 0.17±0.05 2006/09 ...
Page 26
... ASAHI KASEI 1 Date (YY/MM/DD) Revision Reason 06/09/20 00 First Edition MS0544-E-00 MARKING AKM AK4126VQ XXXXXXX XXXXXXX: Date code identifier Revision History Page Contents - 26 - [AK4126] 2006/09 ...
Page 27
... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0544-E-00 IMPORTANT NOTICE - 27 - [AK4126] 2006/09 ...