ak4126 AKM Semiconductor, Inc., ak4126 Datasheet - Page 20

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ak4126

Manufacturer Part Number
ak4126
Description
6ch 192khz / 24-bit Asynchronous Src
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ASAHI KASEI
The change of the clock supplied to the AK4126 is shown in Figure 14. SDTO shows SDTO1, SDTO2 and SDTO3.
The UNLOCK pin outputs “L” when the internal PLL is locked. When the internal PLL is unlocked, the UNLOCK pin
outputs “H”. When PDN pin = “L”, the UNLOCK pin outputs “H”.
MS0544-E-00
Internal Reset Function for Clock Change
UNLOCK pin
(1) Soft mute cycle. (See Table 6)
Note 1. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” from GD before PDN pin goes
Note 2. SMUTE can also be used to remove the unknown data.
E.g. SMT1 pin = “L”, SMT0 pin = “L”, fso = 48kHz
“L”, which will cause the data on SDTO to remain “0”.
Soft mute cycle: 1024/fso = 21.3ms
External clocks
(Input port
PDN pin
(Internal state)
SDTO
SMUTE (Note2,
Att.Level
or Output port)
recommended)
-
0dB
dB
Normal operation
Normal data
Clocks 1
Figure 14. Sequence of changing clocks
(1)
Power-down
Don’t care
Note1
- 20 -
PLL lock &
fs detection
< 100ms
Clocks 2
(1)
Normal operation
Normal data
[AK4126]
2006/09

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