ak4124vf AKM Semiconductor, Inc., ak4124vf Datasheet

Page 1

ASAHI KASEI 192kHz / 24Bit High Performance Asynchronous SRC AK4124 is a stereo digital sample rate converter (SRC). The input sample rate ranges from 8kHz to 216kHz. The output sample rate is from 8kHz to 216kHz. By using the AK4124, ...

Page 2

... ASAHI KASEI T Ordering Guide AK4124VF 40 AKD4124 Evaluation Board for AK4124 T Pin Layout FILT 1 AVSS 2 PDN 3 SMUTE 4 DITHER 5 PLL2 6 ILRCK 7 IBICK 8 SDTI 9 IDIF0 10 IDIF1 11 IDIF2 12 PLL0 13 PLL1 14 UNLOCK 15 MS0288-E-01 +85 C 30pin VSOP (0.65mm pitch) Top View - 2 - [AK4124] AVDD 30 DVSS 29 DVDD 28 OMCLK 27 OLRCK ...

Page 3

ASAHI KASEI T Compatibility with AK4121 Pin 5 Pin 6 THD+N D-Range (A-weighted) Gain between Input and Output Signal fs Master mode for Input PORT MCLK for Master mode (Input PORT) MCLK for Master mode (Output PORT) Output Data Length ...

Page 4

ASAHI KASEI No. Pin Name I/O 1 FILT O PLL Loop Filter Pin 2 AVSS - Analog Ground Pin Power-Down Mode Pin 3 PDN I “H”: Power up, “L”: Power down reset and initializes the control register. Soft Mute Pin ...

Page 5

ASAHI KASEI T Handling of Unused pins The unused digital I/O pins should be processed appropriately as below. Classification Pin Name Analog FILT Digital SMUTE, DITHER IMCLK, OMCLK UNLOCK (AVSS, DVSS=0V; Note 1) Parameter Power Supplies: Analog Digital |AVSS DVSS| ...

Page 6

ASAHI KASEI (Ta=25 C; AVDD=DVDD=3.3V; AVSS=DVSS=0V; data = 24bit; measurement bandwidth = 20Hz ~ FSO/2; unless otherwise specified.) Parameter SRC Characteristics: Resolution Input Sample Rate Output Sample Rate THD+N (Input = 1kHz, 0dBFS, Note 4) FSO/FSI = 44.1kHz/48kHz FSO/FSI = ...

Page 7

ASAHI KASEI (Ta=25 C; AVDD, DVDD=3.0 3.6V) Parameter Digital Filter Passband 0.001dB 0.985 FSO/FSI 0.905 FSO/FSI 0.714 FSO/FSI 0.656 FSO/FSI 0.536 FSO/FSI 0.492 FSO/FSI 0.452 FSO/FSI 0.357 FSO/FSI 0.324 FSO/FSI 0.246 FSO/FSI 0.226 FSO/FSI 0.1667 FSO/FSI Stopband 0.985 FSO/FSI 0.905 ...

Page 8

ASAHI KASEI (Ta=25 C; AVDD, DVDD=3.0 3.6V; C Parameter Master Clock Timing Frequency Pulse Width Low Pulse Width High LRCK for Input data (ILRCK) Frequency Duty Cycle LRCK for Output data (OLRCK) Frequency Duty Cycle Slave Mode Master Mode Audio ...

Page 9

ASAHI KASEI T Timing Diagram MCLK tCLKH LRCK BICK tBCKH LRCK tBLR BICK tLRS SDTO SDTI Note : BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK. MS0288-E-01 1/fCLK tCLKL 1/fs tBCK tBCKL Clock Timing tLRB tBSD tSDS tSDH ...

Page 10

ASAHI KASEI LRCK tMBLR BICK SDTO SDTI Note : BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK. PDN MS0288-E-01 dBCK tBSD tSDS tSDH Audio Interface Timing (Master mode) tPD Power Down & Reset Timing - 10 - [AK4124] ...

Page 11

ASAHI KASEI T System Clock & Audio Interface Format for Input PORT The input port works in master mode or slave mode. An internal system clock is created by the internal PLL using ILRCK (Mode Table 2) ...

Page 12

ASAHI KASEI ILRCK IBICK(32fs) SDTI( IBICK(64fs) Don't Care SDTI(i) 15:MSB, 0:LSB ILRCK ...

Page 13

ASAHI KASEI ILRCK ...

Page 14

ASAHI KASEI OLRCK ...

Page 15

ASAHI KASEI T Soft Mute Operation 1. Manual mode Soft mute operation is performed in the digital domain of the SRC output. Soft mute can be controlled by SMUTE pin. When SMUTE pin goes “H”, the SRC output data is ...

Page 16

ASAHI KASEI T Dither The AK4124 has the dither circuit. The dither circuit adds the dither to the LSB of the output data set with the OBIT1-0 pins by DITHER pin = “H" regardless of the SRC mode or the ...

Page 17

ASAHI KASEI T Internal Reset Function for Clock Change The change of the clock supplied to AK4124 is shown in Figure 13. When the frequency transition occurs gradually without phase change or the clock of output port is changed keeping ...

Page 18

ASAHI KASEI T PLL Loop Filter The C1 and R should be connected in series and attached between FILT pin and AVSS in parallel with C2. Please be careful the noise onto the FILT pin. When using IBICK, the value ...

Page 19

ASAHI KASEI Figure 15 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Input PORT : Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified Output ...

Page 20

ASAHI KASEI Input PORT : Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified Output PORT : Master mode, 24bit MSB justified Dither = OFF 470 1.0n 0.22 Reset fsi 64fsi DSP, uP Note: - AVSS and DVSS of the ...

Page 21

ASAHI KASEI 2. Jitter Tolerance Figure 17 shows the jitter tolerance to ILRCK and IBICK for AK4124. The jitter frequency and the jitter amplitude shown in Figure 17 define the jitter quantity. When the jitter amplitude is 0.01Uipp or less, ...

Page 22

ASAHI KASEI 30pin VSOP (Unit: mm) *9.7 0.1 0 0.22 0.1 0.12 M NOTE: Dimension "*" does not include mold flash. T Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0288-E-01 PACKAGE ...

Page 23

... XXXB : Lot number (X : Digit number Alpha character) YYYYC : Assembly date (Y : Digit number Alpha character) Date (YY/MM/DD) Revision Reason 04/01/26 00 First Edition 04/08/09 01 Add Spec Add Spec MS0288-E-01 MARKING AKM AK4124VF XXXBYYYYC XXXBYYYYC Date code identifier Revision History Page Contents 7 Add FILTER CHARACTERISTICS 21 Add Jitter Tolerance - 23 - [AK4124] 2004/08 ...

Page 24

ASAHI KASEI These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability ...