ak4124vf AKM Semiconductor, Inc., ak4124vf Datasheet - Page 17

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ak4124vf

Manufacturer Part Number
ak4124vf
Description
192khz/ 24bit High Performance Asynchronous Src
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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AK4124VF
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ASAHI KASEI
T Internal Reset Function for Clock Change
The change of the clock supplied to AK4124 is shown in Figure 13. When the frequency transition occurs gradually
without phase change or the clock of output port is changed keeping fso/fsi > 4, the internal reset is not executed and the
SDTO takes time over 100ms to output normal data. To output normal data within 100ms, please reset by PDN pin = “L”.
T UNLOCK pin
The UNLOCK pin outputs “L” when the internal PLL is locked. When the internal PLL is unlocked, the UNLOCK pin
outputs “H”. When PDN pin = “L”, the UNLOCK pin outputs “H”.
MS0288-E-01
Note 1. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” from GD before PDN pin goes
Note 2. SMUTE can also be used to remove the unknown data.
“L”, which will cause the data on SDTO to remain “0”.
External clocks
(Input port
PDN pin
(Internal state)
SDTO
SMUTE (Note2,
Att.Level
or Output port)
recommended)
- dB
0dB
Normal operation
Normal data
Clocks 1
Figure 13. Sequence of changing clocks
1024/fso
Power-down
Don’t care
Note1
- 17 -
PLL lock &
fs detection
< 100ms
Clocks 2
1024/fso
Normal operation
Normal data
[AK4124]
2004/08

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