ak4103a AKM Semiconductor, Inc., ak4103a Datasheet
ak4103a
Available stocks
Related parts for ak4103a
ak4103a Summary of contents
Page 1
... ASAHI KASEI The AK4103A is a digital audio transmitter (DIT) which supports data rate up to 192kHz sample rate operation. The AK4103A supports AES3, IEC60958, S/PDIF & EIAJ CP1201 interface standards. The AK4103A accepts audio data, auxiliary information data and etc, which is then biphase-encoded and driven cable ...
Page 2
... ASAHI KASEI n Block Diagram BICK LRCK SDTI FS0 FS1 FS2 FS3 MS0251-E-00 Prescaler Audio Serial Interface Biphase Encoder CRCC Generator Host Serial Interface - 2 - [AK4103A] TXP TXN 2003/07 ...
Page 3
... BICK 6 LRCK 7 FS0/CSN 8 FS1/CDTI 9 FS2/CCLK 10 FS3/CDTO Comparison AK4103 with AK4103A Function Ambient Temperature CRCC generation by FS3-0 pins CRCC generation by FS3-0 bits MS0251-E-00 24pin VSOP (0.65mm pitch) Top View AK4103 - Synchronous mode X Asynchronous mode X O: Input data is reflected to CRCC. ...
Page 4
... Audio Routing Mode (Transparent Mode) Pin at Synchronous mode 0: Normal mode, 1: Audio routing mode (transparent mode) Power Down & Reset Pin When “L”, the AK4103A is powered-down, TXP/N pins are “L” and the control registers are reset to default values. Master Clock Input Pin ...
Page 5
... VDD -0.3 IIN - VIND -0.3 Ta -40 Tstg -65 Symbol min VDD 4.75 DC CHARACTERISTICS Symbol min IDD VIH 2.4 VIL VOH VDD-1.0 Iout= -8mA) VOH VDD-0.8 VOL Iout= 8mA) VOL Iin - 5 - [AK4103A] max Units 6 VDD+0 150 C typ max Units 5.0 5.25 V typ max Units 0.8 V ...
Page 6
... Units 27.648 MHz 60 % 192 kHz 64fs ...
Page 7
... Clock Timing tBLR tLRB tSDS tSDH Audio Interface Timing (Slave Mode) tSDS tSDH Audio Interface Timing (Master Mode [AK4103A] VIH VIL = tCLKL x fCLK x 100 VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 50%VDD ...
Page 8
... Hi-Z (with pull-down resistor) WRITE/READ Command Input Timing tCSH WRITE Data Input Timing A0 tDCD D7 D6 READ Data Output Timing [AK4103A] VIH VIL VIH VIL VIH * VIL tCSW VIH VIL VIH VIL VIH VIL Hi-Z (with pull-down resistor) VIH ...
Page 9
... ASAHI KASEI CSN CCLK CDTI CDTO D3 PDN MS0251-E-00 tCSW tCSH READ Data Output Timing 2 tPDW Power-down & Reset Timing - 9 - [AK4103A] VIH VIL VIH VIL VIH VIL tCCZ 50%VDD VIL 2003/07 ...
Page 10
... Asynchronous Mode/ Synchronous Mode 1. Asynchronous Mode (software controlled) The AK4103A can be configured in the asynchronous mode by connecting the ANS pin to logic “L”. In this mode the 16 to 24-bit audio samples are accepted through a configured audio serial port, and the channel status and user data through a serial control host interface (SCI) ...
Page 11
... In audio routing mode, the FS0/CSN pin changes definition to AKMODE pin. When set “H” the AK4103A can be configured directly with the AK4112B receiver. When set “L”, it may be used with other non- AKM receivers. Setting the part with TRANS pin = “1” and ANS pin = “0” is illegal and places the chip into a test mode ...
Page 12
BLS C (or U,V) C(R191) LRCK SDTI R190 2 (except I S) SDTI L191 Figure 2. Audio routing mode timing (AKMODE pin = “1”) n Block Start Timing Normal mode In normal mode (TRANS pin = “0”), ...
Page 13
... LRCK Channel 1 BICK Channel 1 C,U Figure 6. Audio routing, DIF modes and 6 MS0251-E- Previous Channel Figure 5. Normal, DIF modes 5 and [AK4103A] 2 S), the C, U and V bits Channel 2 Channel 1 C,U,V Channel 2 Channel Channel 2 Channel 2 ...
Page 14
... In asynchronous mode, DIF2-0 bits are logically ORed with DIF2-0 pins. Audio data format supports 16-24 bits, right justified and left justified modes. The I mode is also supported. The AK4103A can be configured in master and slave modes. Mode ...
Page 15
... Figure 9. Mode 1 Timing Lch Data Figure 10. Mode 2 Timing Lch Data Figure 11. Mode 3 Timing - 15 - [AK4103A Rch Data Rch Data ...
Page 16
... Figure 12. Mode 4, 6 Timing Mode 4: LRCK, BICK: Input Mode 6: LRCK, BICK: Output Lch Data Figure 13. Mode 5, 7 Timing Mode 5: LRCK, BICK: Input Mode 7: LRCK, BICK: Output - 16 - [AK4103A ...
Page 17
... Not Defined 00 Not Defined 00 Not Defined 00 Not Defined 00 For vectoring 00 22.05kHz 00 88.2kHz 00 176.4kHz 00 192kHz 00 24kHz 00 96kHz 00 Not Defined [AK4103A] Byte 4 Bits 6-3 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 0011 0001 0010 1111 2003/07 ...
Page 18
... Frame 0 Figure 14. Block format Figure 15. A biphase-encoded bit stream Audio sample Figure 16. Sub-frame format Preceding state = 0 Preceding state = 1 11101000 11100010 11100100 Table 6. Sub-frame preamble encoding - 18 - [AK4103A] Frame 00010111 00011101 00011011 2003/07 ...
Page 19
... A combination of 330 ohms in parallel with 100 ohms realizes this requirement. The outputs can be set to ground by resetting the device or a software mute. TXP TXN Figure 17. Professional Output Driver Circuit TXP TXN MS0251-E-00 56 0.1u Transformer 330 0.1u Transformer 100 Figure 18. Consumer Output Driver Circuit - 19 - [AK4103A] XLR Connector RCA Phono Connector 2003/07 ...
Page 20
... AK4103A. Figure 19 illustrates the serial data flow associated with SCI read and write operations. C1-0 bits are the chip address. The AK4103A looks for C1-0 bits “11” before responding to the incoming data. R/W is the Read/ Write bit which is “0” for a read operation and “1” for a write operation. The register address contained in A7-0 bits is decoded to select a particular byte of the control register ...
Page 21
Register Map Addr Register Name 00H Clock/Format Control 01H Validity/fs Control A-channel C-bit buffer 02H for Byte 0 A-channel C-bit buffer 03H for Byte 1 A-channel C-bit buffer 04H for Byte 2 A-channel C-bit buffer 05H for Byte 3 ...
Page 22
Register Definitions Addr Register Name 00H Clock/Format Control R/W Default RSTN: Timing Reset. 0: Resets the internal frame and bit counters. Control registers are not initialized. TXP pin is “H” and TXN pin is “L”. In normal mode, BLS ...
Page 23
... CB22 CB21 CB20 R/W R/W R/W R CA30 CA29 CA28 CB30 CB29 CB28 R/W R/W R/W R [AK4103A CA3 CA2 CA1 CA0 CB3 CB2 CB1 CB0 R/W R/W R/W R CA11 CA10 CA9 CA8 CB11 CB10 CB9 CB8 R/W R/W R/W ...
Page 24
Addr Register Name 0AH- A-channel U-bit buffer 0DH for Byte 0-3 0EH- B-channel U-bit buffer 11H for Byte 0-3 R/W Default U0-31: User Data Default: all “0” n Default values of control registers Bits CRCE DIF2-0 CKS1-0 V1 FS3-0 MUTEN ...
Page 25
... ASAHI KASEI 24pin VSOP (Unit: mm) *7.8 0. 0.22 0.1 Seating Plane NOTE: Dimension "*" does not include mold flash. n Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0251-E-00 PACKAGE 13 12 0.65 Detail A 0.10 Epoxy Cu Solder plate (Pb free [AK4103A] 1.25 0.2 A 0.15 0.05 0.1 0.1 0-10 2003/07 ...
Page 26
... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0251-E-00 MARKING AKM AK4103AVF AAXXXX Contents of AAXXXX AA: Lot# XXXX: Date Code IMPORTANT NOTICE - 26 - [AK4103A] 2003/07 ...