at52br3224a ATMEL Corporation, at52br3224a Datasheet - Page 10

• Manufacturer Part Number: at52br3224a
• Description: At52br3224a 32-megabit Flash + 4-megabit/ 8-megabit Sram Stack Memory
• Manufacturer: ATMEL Corporation

10
AT52BR3224A(T)/3228A(T)
RDY/BUSY: For the 32-Mbit Flash memory, an open-drain READY/BUSY output pin provides
another method of detecting the end of a program or erase operation. RDY/BUSY is actively
pulled low during the internal program and erase cycles and is released at the completion of
the cycle. The open-drain connection allows for OR-tying of several devices to the same
RDY/BUSY line. Please see “Status Bit Table” on page 13 for more details.
HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against
inadvertent programs to the device in the following ways: (a) V
(typical), the program function is inhibited. (b) V
V
Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d)
Program inhibit: V
program and erase operations are inhibited for 100 ns.
INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and
control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to V
OUTPUT LEVELS: For the device, output high levels (V
For 2.7V - 3.6V output levels, V
must be regulated to 2.0V ± 10%, while V
power).
CC
sense level, the device will automatically time out 10 ms (typical) before programming. (c)
PP
is less than V
CCQ
ILPP
must be tied to V
. (e) V
CC
PP
must be regulated to 2.7V - 3.0V (for minimum
power-on delay: once V
CC
power-on delay: once V
CC
OH
. For 1.8V - 2.2V output levels, V
) are equal to V
CC
sense: if V
CC
+ 0.6V.
PP
CCQ
has reached 1.65V,
CC
CC
has reached the
- 0.2V (not V
is below 1.8V
3338B–STKD–6/03
CC
CCQ
).