at52br3224a ATMEL Corporation, at52br3224a Datasheet - Page 42

• Manufacturer Part Number: at52br3224a
• Description: At52br3224a 32-megabit Flash + 4-megabit/ 8-megabit Sram Stack Memory
• Manufacturer: ATMEL Corporation

Write Cycle 1 (SWE Controlled)
Write Cycle 2 (SCS1, SCS2 Controlled)
Notes:
42
1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB.
2. t
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after
5. Q (data out) is the same phase with the write data of this write cycle.
6. Q (data out) is the read data of the next address.
7. Transition is measured ± 200 mV from steady state. This parameter is sampled and not 100% tested.
8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby,
AT52BR3224A(T)/3228A(T)
applied.
the SWE transition, outputs remain in a high impedance state.
low for active.
WR
is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle.
DATA OUT
DATA OUT
ADDRESS
ADDRESS
SUB, SLB
SUB, SLB
DATA IN
DATA IN
SCS1
SCS2
SCS1
SCS2
SWE
SWE
HIGH-Z
HIGH-Z
(1),(4),(8)
t
AS
t
AS
t
AS
(1),(4),(8)
t
WHZ
t
HIGH-Z
t
AW
AW
t
t
t
t
WC
BW
(3)(7)
t
CW
WC
BW
t
CW
t
WP
t
WP
DATA VALID
t
t
DW
DW
DATA VALID
t
WR
t
WR
t
t
(2)
DH
DH
t
(2)
OW
(5)
(5)
3338B–STKD–6/03