at52br3224a ATMEL Corporation, at52br3224a Datasheet - Page 14

• Manufacturer Part Number: at52br3224a
• Description: At52br3224a 32-megabit Flash + 4-megabit/ 8-megabit Sram Stack Memory
• Manufacturer: ATMEL Corporation

Command Definition in Hex
Notes:
Absolute Maximum Ratings*
14
Command
Sequence
Read
Chip Erase
Sector Erase
Word Program
Enter Single Pulse
Program Mode
Single Pulse Word
Program
Sector Lockdown
Erase/Program
Suspend
Erase/Program
Resume
Product ID Entry
Product ID Exit
Product ID Exit
Program Protection
Register
Lock Protection
Register - Block B
Status of Block B
Protection
Set Configuration
Register
Temperature under Bias................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground .................................. -0.6V to +6.25V
All Output Voltages
with Respect to Ground ............................ -0.6V to V
Voltage on V
with Respect to Ground .................................. -0.6V to +13.0V
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 18-17 for
4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power
5. Either one of the Product ID Exit commands can be used.
6. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
7. The default state (after power-up) of the configuration register is “00”.
8. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used.
AT52BR3224A(T)/3228A(T)
are don’t care. The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A20 through A11
are don’t care in the word mode.
details).
cycled.
(5)
(5)
PP
Cycles
Bus
1
6
6
4
6
1
6
1
1
3
3
1
4
4
4
4
Addr
Addr
Addr
XXX
XXX
XXX
555
555
555
555
555
555
555
555
555
555
555
1st Bus
Cycle
Data
D
F0
AA
AA
AA
AA
D
AA
AA
AA
AA
AA
AA
AA
B0
30
OUT
IN
(8)
(1)
AAA
AAA
Addr
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
2nd Bus
(2)
(2)
Cycle
CC
+ 0.6V
Data
55
55
55
55
55
55
55
55
55
55
55
Addr
555
555
555
555
555
555
555
555
555
555
555
3rd Bus
Cycle
*NOTICE:
Data
F0
C0
C0
D0
80
80
A0
80
80
90
90
(8)
Addr
Addr
Addr
XXX
555
555
555
555
080
80
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
4th Bus
Cycle
00/01
D
Data
OUT
AA
AA
D
AA
AA
D
X0
IN
IN
(6)
(7)
Addr
AAA
AAA
AAA
AAA
5th Bus
Cycle
Data
55
55
55
55
SA
SA
Addr
3338B–STKD–6/03
555
555
(3)(4)
(3)(4)
6th Bus
Cycle
Data
A0
10
30
60