at52br3224a ATMEL Corporation, at52br3224a Datasheet - Page 41

• Manufacturer Part Number: at52br3224a
• Description: At52br3224a 32-megabit Flash + 4-megabit/ 8-megabit Sram Stack Memory
• Manufacturer: ATMEL Corporation

Timing Diagrams
Read Cycle 1
Read Cycle 2
Read Cycle 3
Notes:
3338B–STKD–6/03
1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
2. SOE = V
3. Transition is measured ± 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
DATA OUT
status.
standby, low for active.
DATA OUT
ADDRESS
SUB, SLB
DATA OUT
ADDRESS
SUB, SLB
SCS1
SCS2
(1),(4)
(1),(2),(4)
(1),(2),(4)
SCS1
SCS2
SOE
IL
.
HIGH-Z
PREVIOUS DATA
t
CLZ
(3)
t
OH
t
BLZ
t
t
t
t
t
AA
ACS
OLZ
CLZ
AA
(3)
(3)
(3)
t
BA
t
ACS
t
OE
t
RC
t
RC
AT52BR3224A(T)/3228A(T)
DATA VALID
DATA VALID
DATA VALID
t
OHZ
t
BHZ
(3)
t
(3)
CHZ
t
t
OH
CHZ
t
OH
(3)
(3)
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