at52br3224a ATMEL Corporation, at52br3224a Datasheet - Page 7

• Manufacturer Part Number: at52br3224a
• Description: At52br3224a 32-megabit Flash + 4-megabit/ 8-megabit Sram Stack Memory
• Manufacturer: ATMEL Corporation

AT52BR3224A(T)/3228A(T)
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified t
cycle
BP
time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a
program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the
erase or program operation was performed successfully.
VPP PIN: The circuitry of the 32-Mbit Flash is designed so that the device cannot be pro-
grammed or erased if the V
voltage is less that 0.4V. When V
is at 0.9V or above, normal
PP
PP
program and erase operations can be performed. The VPP pin cannot be left floating.
PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a
program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 13
and the following four sections describe the function of these bits. To provide greater flexibility
for system designers, the device contains a programmable configuration register. The configu-
ration register allows the user to specify the status bit operation. The configuration register can
be set to one of two different values, “00” or “01”. If the configuration register is set to “00”, the
part will automatically return to the read mode after a successful program or erase operation. If
the configuration register is set to a “01”, a Product ID Exit command must be given after a
successful program or erase operation before the part will return to the read mode. It is impor-
tant to note that whether the configuration register is set to a “00” or to a “01”, any
unsuccessful program or erase operation requires using the Product ID Exit command to
return the device to read mode. The default value (after power-up) for the configuration regis-
ter is “00”. Using the four-bus cycle Set Configuration Register command as shown in the
“Command Definition in Hex” table on page 14, the value of the configuration register can be
changed. Voltages applied to the RESET pin will not alter the value of the configuration regis-
ter. The value of the configuration register will affect the operation of the I/O7 status bit as
described below.
DATA POLLING: The device features Data Polling to indicate the end of a program cycle. If
the status configuration register is set to a “00”, during a program cycle an attempted read of
the last word loaded will result in the complement of the loaded data on I/O7. Once the pro-
gram cycle has been completed, true data is valid on all outputs and the next cycle may begin.
During a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7.
Once the program or erase cycle has completed, true data will be read from the device. Data
Polling may begin at any time during the program cycle. Please see “Status Bit Table” on page
13 for more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has com-
pleted a program or erase operation. Once I/O7 has gone high, status information on the other
pins can be checked.
The Data Polling status bit must be used in conjunction with the erase/program and V
status
PP
bit as shown in the algorithm in Figures 1 and 2 on page 11.
7
3338B–STKD–6/03