at52br3224a ATMEL Corporation, at52br3224a Datasheet - Page 11

• Manufacturer Part Number: at52br3224a
• Description: At52br3224a 32-megabit Flash + 4-megabit/ 8-megabit Sram Stack Memory
• Manufacturer: ATMEL Corporation

Figure 1. Data Polling Algorithm
(Configuration Register = 00)
Notes:
3338B–STKD–6/03
NO
1. VA = Valid address for programming. During a sec-
2. I/O7 should be rechecked even if I/O5 = “1”
Successful, Write
tor erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
because I/O7 may change simultaneously with
I/O5.
Read I/O7 - I/O0
Read I/O7 - I/O0
Program/Erase
I/O3, I/O5 = 1?
Exit Command
Operation Not
I/O7 = Data?
Product ID
I/O7 = Data?
Addr = VA
Addr = VA
START
NO
YES
NO
YES
YES
Program/Erase
Read Mode
Successful,
Operation
Device in
Figure 2. Data Polling Algorithm
(Configuration Register = 01)
Note:
NO
AT52BR3224A(T)/3228A(T)
1. VA = Valid address for programming. During a sec-
Successful, Write
tor erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Program/Erase
I/O3, I/O5 = 1?
Exit Command
Operation Not
Toggle Bit =
Toggle Bit =
Product ID
Toggle?
Toggle?
START
Twice
YES
YES
YES
NO
NO
Program/Erase
Successful
Operation
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