m36l0t7050b0 STMicroelectronics, m36l0t7050b0 Datasheet - Page 6

• Manufacturer Part Number: m36l0t7050b0
• Description: 128mbit Multiple Bank, Multi-level, Burst Flash Memory 32mbit 2m X16 Psram, Multi-chip Package
• Manufacturer: STMicroelectronics

M36L0T7050T0, M36L0T7050B0
SIGNAL DESCRIPTIONS
See
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A22). Addresses
are common inputs for the Flash Memory and the
PSRAM components. The other lines (A21-A22)
are inputs for the Flash Memory component only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur-
ing Bus Write operations they control the com-
mands sent to the Command Interface of the Flash
memory Program/Erase Controller or they select
the cells to access in the PSRAM.
The Flash memory component is accessed
through the Chip Enable signal (E
the Write Enable (W
accessed through two Chip Enable signals (E1
and E2
Data Input/Output (DQ0-DQ15). In the Flash
memory the Data I/O output the data stored at the
selected address during a Bus Read operation or
input a command or the data to be programmed
during a Write Bus operation.
In the PSRAM the Upper Byte Data Inputs/Out-
puts, DQ8-DQ15, carry the data to or from the up-
per part of the selected address during a Write or
Read operation, when Upper Byte Enable (UB
driven Low.
The Lower Byte Data Inputs/Outputs, DQ0-DQ7,
carry the data to or from the lower part of the se-
lected address during a Write or Read operation,
when Lower Byte Enable (LB
Flash Chip Enable (E
activates the memory control logic, input buffers,
decoders and sense amplifiers. When Chip En-
able is Low, V
is in active mode. When Chip Enable is at V
Flash memory is deselected, the outputs are high
impedance and the power consumption is reduced
to the standby level.
Flash Output Enable (G
input controls data output during Flash memory
Bus Read operations.
Flash Write Enable (
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WP
input that gives an additional hardware protection
for each block. When Write Protect is Low, V
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at High, V
disabled and the Locked-Down blocks can be
6/18
Figure 2., Logic Diagram
P
) and the Write Enable signal (W
IL
, and Reset is High, V
F
) signal, while the PSRAM is
W
F
F
). The Chip Enable input
). The
F
F
). The Output Enable
). Write Protect is an
P
and
) is driven Low.
IH
Table 1., Signal
Write
F
, Lock-Down is
) and through
IH
, the device
P
A0-A20
).
Enable
IH
P
the
) is
IL
P
,
locked or unlocked. (See the Lock Status Table in
the M30L0T7000T0 datasheet).
Flash Reset (RP
hardware reset of the memory. When Reset is at
V
high impedance and the current consumption is
reduced to the Reset Supply Current I
Table 7., Flash DC Characteristics -
the value of I
Locked state and the Configuration Register is re-
set. When Reset is at V
operation. Exiting Reset mode the device enters
Asynchronous Read mode, but a negative transi-
tion of Chip Enable or Latch Enable is required to
ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to V
(refer to
tics -
Flash Latch Enable (L
the address bits on its rising edge. The address
latch is transparent when Latch Enable is Low, V
and it is inhibited when Latch Enable is High, V
Latch Enable can be kept Low (also at board level)
when the Latch Enable function is not required or
supported.
Flash Clock (K
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (rising or falling, accord-
ing to the configuration settings) when Latch En-
able is at V
Asynchronous Read and in write operations.
Flash Wait (WAIT
nal used during Synchronous Read to indicate
whether the data on the output bus are valid. This
output is high impedance when Flash Chip Enable
is at V
ured to be active during the wait cycle or one clock
cycle in advance. The WAIT
by Output Enable.
Chip Enable (E1
Chip Enable, E1
chine, address buffers and decoders, allowing
Read and Write operations to be performed. When
de-asserted (High), all other pins are ignored, and
the device is put, automatically, in low-power
Standby mode.
Chip Enable (E2
the device in Power-down mode (Deep Power-
Down, PAR and Standby) when it is driven Low.
One of these, Deep Power-Down mode, is the low-
est power mode.
Output Enable (G
provides a high speed tri-state control, allowing
IL
, the memory is in Reset mode: the outputs are
Voltages).
IH
Table 8., Flash Memory DC Characteris-
or Flash Reset is at V
DD2
IL
F
P
. Clock is don't care during
. After Reset all blocks are in the
). The Clock input synchronizes
F
P
P
, activates the memory state ma-
). The Reset input provides a
F
). When asserted (Low), the
). The Chip Enable, E2
P
). WAIT is a Flash output sig-
). The Output Enable, G
F
IH
). Latch Enable latches
, the device is in normal
F
IL
signal is not gated
. It can be config-
Currents, for
DD2
. Refer to
P
, puts
RPH
IH
IL
P
,
.
,