cdp1883c Intersil Corporation, cdp1883c Datasheet - Page 4

• Manufacturer Part Number: cdp1883c
• Description: Cmos 7-bit Latch And Decoder Memory Interfaces
• Manufacturer: Intersil Corporation

Signal Descriptions/Pin Functions
CLOCK: Latch Input Control - a high on the clock input will
allow data to pass through the latch to the output pin. Data is
latched on the high-to-low transition of the clock input. This
pin is connected to TPA in CDP1800-series systems and tied
to V
MA0 - MA4: Address inputs to the high-byte address
latches.
MA5 - MA6: High byte address inputs decoded to produce
chip selects CS0 - CS3.
CE: CHIP ENABLE input - A low on this pin will enable the
chip select decoder. A high on this pin forces CS0, CS1,
CS2, and CS3 outputs to a high (false) state.
A8 - A12: Latched high-byte address outputs.
CS0 - CS3: One of four latched and decoded Chip Select
outputs.
V
Dynamic Electrical Specifications
Minimum Setup Time,
Memory Address to CLOCK
Minimum Hold Time,
Memory Address After CLOCK
Minimum CLOCK Pulse Width
PROPAGATION DELAY TIMES
Chip Enable to Chip Select
CLOCK to Chip Select
DD
CE
0
0
0
0
0
1
DD
, V
SS
for other applications.
CLK
: Power and ground pins, respectively.
X
1
1
1
1
0
INPUTS
MA5
PARAMETER
X
X
0
1
0
1
TRUTH TABLE
MA6
0
0
1
1
X
X
CS0
0
1
1
1
1
Previous State
CS1
t
t
t
t
t
CLMA
CECS
MACL
CLCS
CLCL
OUTPUTS
1
0
1
1
1
T
See Figure 1
A
= -40
CDP1883, CDP1883C
CS2
1
1
0
1
1
o
C to +85
V
(V)
10
10
10
10
10
DD
5
5
5
5
5
CS3
1
1
1
0
1
o
C, V
4-132
MIN
-
-
-
-
-
-
-
-
-
-
DD
X = Don’t Care
Application Information
The CDP1883 and CDP1883C can be interfaced, without
external components, with CDP1800-series microprocessor
systems. These microprocessors feature a multiplexed
address bus and provide an address latch signal (TPA) that
is used as the clock input of the CDP1883. See Figure 2 and
Figure 3.
This signal is used to latch 7 bits of the high-order address.
The lower five high-order address inputs are latched and
held to be used with the eight lower-order address inputs to
access an 8K x 8-bit memory. The two upper high-order
address inputs are latched and decoded for use as chip
selects.
The latched address and decoding functions of the
CDP1883 and CDP1883C allow them to operate with 32K-
byte memory systems. In addition, smaller memory systems
can be configured with 4K x 8-bit or smaller memories, or a
mix of memory sizes up to 8K x 8-bit.
(NOTE 1)
CE
5%, t
CDP1883
X
X
X
TYP
100
10
50
25
75
45
65
8
8
8
R
, t
F
INPUTS
= 20ns, V
(NOTE 2)
CLK
1
1
0
MAX
150
100
175
125
35
25
25
25
75
40
IH
MA0 - 4
TRUTH TABLE
= 0.7 V
MIN
1
0
X
-
-
-
-
-
-
-
-
-
-
DD
CDP1883C
(NOTE 1)
, V
TYP
100
10
50
75
IL
8
-
-
-
-
-
= 0.3 V
Previous State
OUTPUTS
A8 - A12
(NOTE 2)
DD
MAX
150
175
35
25
75
1
0
-
-
-
-
-
, C
L
= 100pF.
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns