gds1110bb Intel Corporation, gds1110bb Datasheet - Page 3

• Manufacturer Part Number: gds1110bb
• Description: Intel-r Strongarm Sa-1110 Microprocessor
• Manufacturer: Intel Corporation

Intel
Intel
SA-1110 Brief Datasheet
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StrongARM SA-1110 CPU
StrongARM SA-1110 System Control Functions
further power savings. For embedded applications, the SA-1110 offers high-performance
computing at consumer electronics pricing with MIPS-per-dollar and MIPS-per-watt advantages.
The SA-1110 delivers in price/performance and power/performance, making it a chice for portable
and embedded applications. The SA-1110 differs from the Intel
Microprocessor (SA-1100) only in the features of its memory and PCMCIA controller.
The SA-1110 CPU implements the ARM V4 architecture as defined in the ARM Architecture
Reference Manual. Architectural enhancements beyond the ARM V4 are implemented through use
of coprocessor 15. Control register reads and writes to coprocessor 15 provide access to MMU,
cache, and write and read buffer control registers.
The SA-1110 MMUs provide separate 32-entry translation look-aside buffers (TLBs) for the
instruction and data streams. Each of the 32 entries may map segments, large pages, or small pages
in memory. The SA-1110 contains 16 Kbyte of instruction cache and 8 Kbyte of data cache. In
addition to this, a minicache is provided to prevent periodic large data transfers from thrashing the
main data cache. The data and instruction caches are implemented as 32-byte blocks, and provide
32-way associativity, with victim replacement performed in a round-robin fashion. The minicache
is 16 entries and is 2-way set associative, implementing the least-recently-used (LRU) algorithm
for victim replacement.
The SA-1110 also provides a write buffer and a read buffer. The read buffer allows critical data to
be prefetched under software control, preventing pipeline stalls from occurring during external
memory reads. The write buffer provides additional system efficiency by buffering between the
CPU clock frequency and the actual bus speed when data is being written by the CPU to external
memory. The write buffer is eight entries, and allows each entry to contain between 1 and 16 bytes.
The read buffer is four entries, and allows each entry to contain 1, 4, or 8 words.
The SA-1110 provides timers, sophisticated power-management functions, interrupt control, reset
control, and on-chip oscillators and PLLs for clock generation. There are 28 general-purpose I/Os,
which can, in addition to being directly read or written by the CPU, be programmed to generate an
interrupt.
The real-time clock and trim logic run off the 32.768-kHz crystal and provide accuracy of
seconds/month.
The 32-bit OS timer runs off the 3.686-MHz oscillator and is used in companion with the four
32-bit timer match registers. One of the four match registers is used specifically as a watchdog
timer interrupt, preventing system lockout from occurring when software or hardware is trapped in
a loop state with no controlled exit. The remaining three registers are available for use as interval
timers or other user-defined purposes.
The interrupt controller routes all interrupt sources to either an FIQ or IRQ request to the CPU.
IRQ is a lower priority interrupt and may be interrupted by FIQ. FIQ is unique to the ARM
architecture and allows fast servicing to occur on specific interrupt sources, as determined by the
user. There are two levels in servicing interrupts. The first level alerts the user or operating system
to what specific module on the SA-1110 experienced an interrupt condition. The second level
provides information on what event within the specific module caused an interrupt to be flagged.
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StrongARM SA-1100
SA-1110
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