u3745bm ATMEL Corporation, u3745bm Datasheet - Page 10

• Manufacturer Part Number: u3745bm
• Description: Receiver
• Manufacturer: ATMEL Corporation

Polling Circuit and Control Logic
Basic Clock Cycle of the
Digital Circuitry
10
U3745BM
The receiver is designed to consume less than 1 mA while being sensitive to signals
from a corresponding transmitter. This is achieved via the polling circuit. This circuit
enables the signal path periodically for a short time. During this time the bit check logic
verifies the presence of a valid transmitter signal. Only if a valid signal is detected the
receiver remains active and transfers the data to the connected microcontroller. If there
is no valid signal present, the receiver is in sleep mode most of the time resulting in low
current consumption. This condition is called polling mode. A connected microcontroller
is disabled during that time.
All relevant parameters of the polling logic can be configured by the connected micro-
controller. This flexibility enables the user to meet the specifications in terms of current
consumption, system response time, data rate etc.
Regarding the number of connection wires to the µC, the receiver is very flexible. It can
be either operated by a single bi-directional line to save ports to the connected micro-
controller, or it can be operated by up to three uni-directional ports.
The complete timing of the digital circuitry and the analog filtering is derived from one
clock. According to Figure 6, this clock cycle T
(XTO) in combination with a divider. The division factor is controlled by the logical state
at pin MODE. According to section “RF Front End”, the frequency of the crystal oscillator
(f
of the local oscillator (f
Figure 6. Generation of the Basic Clock Cycle
Pin MODE can now be set in accordance with the desired clock cycle T
the following application-relevant parameters:
•
•
•
•
•
Most applications are dominated by two transmission frequencies: f
mainly used in the USA, f
T
each parameter.
XTO
Clk
-dependent parameters, the electrical characteristics display three conditions for
Timing of the polling circuit including bit check
Timing of analog and digital signal processing
Timing of register programming
Frequency of the reset marker
F filter center frequency (f
) is defined by the RF input signal (f
LO
).
Send
:14/:10
= 433.92 MHz in Europe. In order to ease the usage of all
Divider
IF0
XTO
)
T
f
Clk
XTO
RFin
16
15
14
MODE
DVCC
XTO
) which also defines the operating frequency
Clk
H: Europe (:14)
L : USA (:10)
is derived from the crystal oscillator
Send
Clk
= 315 MHz is
4663A–RKE–06/03
. T
Clk
controls