u3745bm ATMEL Corporation, u3745bm Datasheet - Page 13

• Manufacturer Part Number: u3745bm
• Description: Receiver
• Manufacturer: ATMEL Corporation

Figure 8. Timing Diagram for a Completely Successful Bit Check
Bit Check Mode
Configuring the Bit Check
4663A–RKE–06/03
( Number of checked Bits: 3 )
Enable IC
Dem_out
DATA
Bit check
Polling - Mode
In bit check mode, the incoming data stream is examined to distinguish between a valid
signal from a corresponding transmitter and signals due to noise. This is done by subse-
quent time frame checks where the distances between 2 signal edges are continuously
compared to a programmable time window. The maximum count of this edge-to-edge
test, before the receiver switches to receiving, mode is also programmable.
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks
are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation
schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the
variable N
checks respectively. If N
switch to the receiving mode due to noise. In the presence of a valid transmitter signal,
the bit check takes less time if N
check time is not dependent on N
tested successfully and the data signal is transferred to Pin DATA.
According to Figure 9, the time window for the bit check is defined by two separate time
limits. If the edge-to-edge time t
upper bit check limit T
t
mode.
Figure 9. Valid Time Window for Bit Check
For best noise immunity it is recommended to use a low span between T
T
preburst. A ‘11111...’ or a ‘10101...’ sequence in Manchester or Bi-phase is a good
choice in this regard. A good compromise between receiver sensitivity and susceptibility
to noise is a time window of ± 25% regarding the expected edge-to-edge time t
preburst patterns that contain various edge-to-edge time periods, the bit check limits
must be programmed according to the required span.
The bit check limits are determined by means of the formula below:
ee
Lim_max
exceeds T
. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter
1/2 Bit
Bitcheck
Lim_max
1/2 Bit
in the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge
Dem_out
, the bit check will be terminated and the receiver switches to sleep
1/2 Bit
Lim_max
Bit check ok
Bitcheck
1/2 Bit
, the check will be continued. If t
ee
is set to a higher value, the receiver is less likely to
Bitcheck
1/2 Bit
is in between the lower bit check limit T
Bitcheck
T
T
Lim_min
Lim_max
t
ee
1/2 Bit
is set to a lower value. In polling mode, the bit
. Figure 8 shows an example where 3 bits are
1/f
Sig
Receiving mode
ee
is smaller than T
U3745BM
Lim_min
Lim_min
ee
Lim_min
and the
. Using
and
13
or