u3745bm ATMEL Corporation, u3745bm Datasheet - Page 12

• Manufacturer Part Number: u3745bm
• Description: Receiver
• Manufacturer: ATMEL Corporation

Figure 7. Polling Mode Flow Chart
12
U3745BM
NO
(T
Sleep mode:
All circuits for signal processing
are disabled. Only XTO and
Start-up mode:
The signal processing circuits are
enabled. After the start-up time
condition and ready to receive.
The incomming data stream is
analyzed. If the timing indicates a
valid transmitter signal, the receiver
is set to receiving mode. Otherwise
it is set to Sleep mode.
Receiving mode:
The receiver is turned on
permanently and passes the data
be set to Sleep mode through an
ENABLE.
polling logic are enabled.
I
T
I
T
OFF command via pin DATA or
I
I
stream to the connected mC. It can
T
Bit check mode:
S
S
S
S
Startup
Bitcheck
Sleep
= I
= I
= I
= I
Startup
SON
SON
SON
SON
= Sleep x X
) all circuits are in stable
Bitcheck
OFF command
OK ?
Sleep
XSleep
as long as every bit check is OK. If the bit check fails once, this bit is set back to 0 auto-
matically resulting in a regular sleep time. This functionality can be used to save current
in presence of a modulated disturber similar to an expected transmitter signal. The con-
nected microcontroller is rarely activated in that condition. If the disturber disappears,
the receiver switches back to regular polling and is again sensitive to appropriate trans-
mitter signals.
According to Table 7, the highest register value of Sleep sets the receiver to a perma-
nent sleep condition. The receiver remains in that condition until another value for Sleep
is programmed into the OPMODE register. This function is desirable where several
devices share a single data line.
YES
x 1024 x T
Temp
= 1 implies the temporary extension factor. The extended sleep time is used
Clk
T
Sleep:
T
Bitcheck
X
Startup
Sleep
T
Clk
:
:
:
:
5-bit word defined by Sleep0 to
Sleep4 in OPMODE register
Extension factor defined by XSleep
Basic clock cycle defined by f
and Pin MODE
Is defined by the selected baud rate
range and T
is defined by Baud0 and Baud1 in
the OPMODE register.
Depends on the result of the bitcheck
the number of bits to be
checked (N
utilized data rate.
If the bitcheck fails, the average
time period for that check depends
on the selected baud rate range and
on T
defined by Baud0 and Baud1 in the
OPMODE register.
according to Table 8
If the bitcheck is ok, T
Clk
.The baud rate range is
Bitchecked
Clk
. The baud rate range
) and on the
Bitcheck
depends on
XTO
Temp
4663A–RKE–06/03