u3745bm ATMEL Corporation, u3745bm Datasheet - Page 14

• Manufacturer Part Number: u3745bm
• Description: Receiver
• Manufacturer: ATMEL Corporation

Figure 10. Timing Diagram During Bit Check
Figure 11. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
14
Dem_out
Bit check
Bit check Counter
( Lim_min = 14, Lim_max = 24 )
Enable IC
Bit check
Enable IC
Dem_out
Bit check Counter
( Lim_min = 14, Lim_max = 24 )
U3745BM
Startup Mode
T
0
Startup
0
1
T
T
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using the above formulas, Lim_min and Lim_max can be determined according to the
required T
T
according to the section “Receiving Mode”. Due to this, the lower limit should be set to
Lim_min ³ 10. The maximum value of the upper limit is Lim_max = 63.
Figure 10, Figure 11 and Figure 12 illustrate the bit check for the default bit check limits
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits
are enabled during T
ing that period. When the bit check becomes active, the bit check counter is clocked with
the cycle T
Figure 10 shows how the bit check proceeds if the bit-check counter value CV_Lim is
within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
Figure 12, the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit
check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 13.
1
Lim_min
Lim_max
Lim_max
2 3 4 5 6
2 3 4 5 6
T
= Lim_min ´ T
XClk
= (Lim_max –1) ´ T
is T
1
Lim_min
XClk
Bit check Mode
7 8 1
XClk
2
.
3
. The minimum edge-to-edge time t
4 5
, T
2
3
1/2 Bit
Lim_max
6 7 8 9
4 5
Startup
XClk
Bit check failed ( CV_Lim < Lim_min )
6 7 8 9
. The output of the demodulator (Dem_out) is undefined dur-
10
1/2 Bit
and T
XClk
11 12
10
11 12 13 14
XClk
. The time resolution when defining T
15 16 17 18
Bit check ok
Sleep Mode
0
1 2 3 4 5 6
ee
(t
DATA_L_min
1/2 Bit
7 8 9 10 11 12 13 14 15
, t
DATA_H_min
Bit check ok
4663A–RKE–06/03
) is defined
1 2 3 4
Lim_min
1/2 Bit
and