m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 27
m28529-12
Manufacturer Part Number
m28529-12
Description
Inverse Multiplexing For Atm Ima Family
Manufacturer
Mindspeed Technologies
Datasheet
1.M28529-12.pdf
(309 pages)
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1.2.2
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1.2.3
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1.2.4
1.2.4.1
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1.2.4.2
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28529-DSH-001-K
Source Loopback
Far End Line Loopback
IMA Line Loopback
IMA System Loopback
ICP Cell Access
IEEE 1149.1 JTAG Interface
Supports ATM cell interface for:
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Performs single-bit HEC correction and single- or multiple-bit detection
Inserts headers and generates HEC
Direct connection to external Mindspeed components for:
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Byte-level or bit-level cell delineation
Asynchronous SRAM-like interface mode
8-bit data bus
Open-drain interrupt output
Open-drain ready output
Up to 66 MHz operation
All control registers are read/write
ATM-side UTOPIA Interface:
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Circuit-based physical layer
Cell-based physical layer
T1/E1
xDSL
General purpose mode
8/16-bit UTOPIA Level 2 Slave
Up to 50 MHz operation
Support for dual Clav and Enable signals
Supports 32 ATM addresses
Diagnostics/Loopbacks
Cell Delineation Section
Control and Status
Microprocessor Interface
ATM Interface
Mindspeed Proprietary and Confidential
Mindspeed Technologies
®
Functional Description
12
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