m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 28

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

1.2.4.3
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1.2.4.4
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1.3
The M2852x family of devices provides system designers with a complete integrated IMA solution for up to 32
ports. All devices include a Transmission Convergence block to perform cell delineation, 512 K internal RAM to
meet ATM forum requirements for differential delay compensation and a dual mode (UTOPIA or Serial) PHY layer
interface. Source code for all required software functions is available from Mindspeed. The M28529 supports 32
IMA groups with 1-32 links per group.
The TC block is capable of bit level cell delineation, which allows for direct connection DSL serial data streams
without a frame sync pulse. Individual ports can be operated in a 'pass thru' mode without the IMA overhead.
The M28529 provides direct connection to 32 serial/interleaved highway links or a PHY side UTOPIA bus. In
addition, an external memory bus allows the differential delay memory to access up to 2 Mbytes of external
RAM.The M28529 supports both version 1.0 and 1.1 of IMA standard AF-PHY-0086.001
28529-DSH-001-K
PHY-side UTOPIA Interface:
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Serial Interface
Interleaved Highway
Up to 33 MHz operation
Summary interrupt indications
Configuration of interrupt enables
One-second counter latching
Counters for:
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8/16-bit UTOPIA Level 2 Master
Supports 32 ports via dual CLAV and Enable lines
LOCD events
Corrected HEC errors
Uncorrected HEC errors
Transmitted cells
Matching received cells
Non-matching received cells
Idle cell receive
PHY Interfaces
Counters/Status Register Section
General Description
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Functional Description
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