m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 277
m28529-12
Manufacturer Part Number
m28529-12
Description
Inverse Multiplexing For Atm Ima Family
Manufacturer
Mindspeed Technologies
Datasheet
1.M28529-12.pdf
(309 pages)
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3.4.6
Figures 3-22
PHY-side UTOPIA interface.
Figure 3-22. PHY-side UTOPIA Transmit Timing
Table 3-17.
28529-DSH-001-K
Footnote:
(1) This clock is a divide-by-2 of IMA_SysClk.
General Note:
1. Timing applies with 0-50pF loads on the outputs.
Symbol
t
per
t
phyUTxData[15:0]
duty
t
t
t
pd
s
h
phyUTxAddr[4:0]
(1)
phyUTxSOC
through
phyUtxEnb*
phyUTxClav
phyUTxPrty
phyUTxClk
PHY-side UTOPIA Transmit Timing Parameters
PHY-Side Interface Timing (UTOPIA)
UTOPIA transmit clock period
UTOPIA transmit clock dutycycle
Setup to phyutxclk rise edge
Hold from phyutxclk rise edge
Enable from phyutxclk fall edge
3-23
and
Tables 3-17
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Parameter
through
3-18
show the timing requirements and characteristics of the
t
t
t
t
t
pd
pd
pd
pd
pd
t
s
t
per
®
Minimum
30.3
-5
8
1
t
h
Typical
50
Product Specification
Maximum
7
Units
ns
ns
%
ns
ns
262
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