k4x51163pc Samsung Semiconductor, Inc., k4x51163pc Datasheet - Page 11

• Manufacturer Part Number: k4x51163pc
• Description: 32m X16 Mobile-ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
Note :
1. It has +/- 5
2. DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request.
3. IDD specifications are tested after the device is properly intialized.
4. Input slew rate is 1V/ns.
5. Definitions for IDD: LOW is defined as V
K4X51163PC - L(F)E/G
Operating Current
(One Bank Active)
Precharge Standby Current in
power-down mode
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Deep Power Down Current
Please contact Samsung for more information.
Parameter
°C
tolerance.
HIGH is defined as V
STABLE is defined as inputs stable at a HIGH or LOW level ;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ;
Symbol
IDD2PS
IDD2NS
IDD3PS
IDD3NS
IDD4W
IDD2N
IDD3N
IDD4R
IDD8*
IDD2P
IDD3P
IDD0
IDD5
IDD6
2
tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH; CS is HIGH between valid commands;
address inputs are SWITCHING; data bus inputs are STABLE
all banks idle, CKE is LOW; CS is HIGH, tCK = t CKmin ; address and control inputs are
SWITCHING; data bus inputs are STABLE
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control
inputs are SWITCHING; data bus inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, tCK = t CKmin ;address and control inputs are
SWITCHING; data bus inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control
inputs are SWITCHING; data bus inputs are STABLE
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin ;address and control inputs are
SWITCHING; data bus inputs are STABLE
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;address and control
inputs are SWITCHING; data bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin ;address and control inputs
are SWITCHING; data bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
one bank active; BL = 4; CL = 3; tCK = tCKmin ; continuous read bursts; I OUT = 0 mA
address inputs are SWITCHING; 50% data change each burst transfer
one bank active; BL = 4; tCK = tCKmin ; continuous write bursts;address inputs are
SWITCHING; 50% data change each burst transfer
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH;address and control inputs
are SWITCHING; data bus inputs are STABLE
CKE is LOW; tCK = tCKmin ;
Extended Mode Register set to all 0’s;
address and control inputs are STABLE; data bus inputs
are STABLE
Address and control inputs are STABLE; data bus inputs are STABLE
IN
IN
≥
≤
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
0.9 * VDDQ ;
0.1 * VDDQ ;
Test Condition
SS
= 0V, Tc = -25 to 85°C)
-G
-E
TCSR
Full Array
Full Array
1/2 Array
1/4 Array
1/2 Array
1/4 Array
Mobile-DDR SDRAM
DDR266
45*
115
100
150
300
270
255
250
220
205
80
12
25
20
8
1
0.3
0.3
10
6
3
DDR222
February 2006
135
600
500
450
500
400
350
70
10
20
15
95
90
85
7
Unit
mA
mA
mA
mA
mA
mA
mA
uA
uA
°C