k4x51163pc Samsung Semiconductor, Inc., k4x51163pc Datasheet - Page 6

• Manufacturer Part Number: k4x51163pc
• Description: 32m X16 Mobile-ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4X51163PC - L(F)E/G
Mode Register Definition
Mode Register Set(MRS)
The mode register is designed to support the various operating modes of DDR SDRAM. It includes Cas latency, addressing mode,
burst length, test mode and vendor specific options to make DDR SDRAM useful for variety of applications. The default value of the
mode register is not defined, therefore the mode register must be written in the power up sequence of DDR SDRAM. The mode reg-
ister is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to
writing into the mode register). The states of address pins A0 ~ A12 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE
going low are written in the mode register. Two clock cycles are required to complete the write operation in the mode register. Even if
the power-up sequence is finished and some read or write operation is executed afterward, the mode register contents can be
changed with the same command and two clock cycles. This command must be issued only when all banks are in the idle state. If
mode register is changed, extended mode register automatically is reset and come into default state. So extended mode register
must be set again. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,
addressing mode uses A3, Cas latency(read latency from column address) uses A4 ~ A6, A7 ~ A12 is used for test mode. BA0 and
BA1 must be set to low for proper MRS operation.
Note :
RFU(Reserved for future use) should stay "0" during MRS cycle
BA1
0
BA0
0
A12 ~ A10/AP
RFU*
A9
0
Figure.2 Mode Register Set
A6
0
0
0
0
1
1
1
1
A8
0
A5
0
0
1
1
0
0
1
1
A7
0
A4
0
1
0
1
0
1
0
1
A6
CAS Latency
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A5
2
3
A
0
1
A4
3
Burst Type
Mobile-DDR SDRAM
A3
BT
Sequential
Interleave
A
A2
0
0
0
0
1
1
1
1
2
Burst Length
A
A1
0
0
1
1
0
0
1
1
1
A
A0
0
1
0
1
0
1
0
1
February 2006
0
Address Bus
Mode Register
Burst Length
Reserved
Reserved
Reserved
Reserved
16
2
4
8