k4x51163pc Samsung Semiconductor, Inc., k4x51163pc Datasheet - Page 8

• Manufacturer Part Number: k4x51163pc
• Description: 32m X16 Mobile-ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4X51163PC - L(F)E/G
and the EMRS command needs to be issued only when either PASR or DS is used. The default state without EMRS command
issued is half driver strength, and Full array refreshed. The extended mode register is written by asserting low on CS, RAS, CAS,
WE and high on BA1 ,low on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the
extended mode register). The state of address pins A0 ~ A12 in the same cycle as CS, RAS, CAS and WE going low is written in the
extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the
power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed
with the same command and two clock cycles. But this command must be issued only when all banks are in the idle state. A0 - A2
are used for partial array self refresh and A5 - A6 are used for driver strength control. "High" on BA1 and"Low" on BA0 are used for
EMRS. All the other address pins except A0,A1,A2,A5,A6, BA1, BA0 must be set to low for proper EMRS operation. Refer to the
table for specific codes.
Extended MRS for PASR(Partial Array Self Refresh) &
DS(Driver Strength Control)
Note :
RFU(Reserved for future use) should stay "0" during EMRS cycle
Extended Mode Register Set(EMRS)
BA1
The extended mode register is designed to support partial array self refresh or driver strength control. EMRS cycle is not mandatory
1
BA0
0
A
0
0
1
1
6
A
0
1
0
1
A12 ~ A10/AP
5
RFU*
Driver Strength
DS
Full
1/2
1/4
1/8
Figure.3 Extended Mode Register Set
A9
0
A8
0
Self refresh cycle is controlled
automatically by internal tem-
perature sensor and control cir-
cuit according to the three
temperature ranges ; 45 °C and
85 °C
A7
0
Internal TCSR
A6
DS
A5
A4
RFU*
A3
Mobile-DDR SDRAM
A
0
0
0
0
1
1
1
1
2
A2
A
0
0
1
1
0
0
1
1
1
PASR
A1
A
0
1
0
1
0
1
0
1
0
PASR
A0
Refreshed Area
1/2 of Full Array
1/4 of Full Array
February 2006
Full Array
Reserved
Reserved
Reserved
Reserved
Reserved
Address Bus
Mode Register