k4x51163pc Samsung Semiconductor, Inc., k4x51163pc Datasheet - Page 15

• Manufacturer Part Number: k4x51163pc
• Description: 32m X16 Mobile-ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4X51163PC - L(F)E/G
Note :
1. Input Setup/Hold Slew Rate Derating
2. Minimum 3CLK of tDAL(= tWR + tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP.
3. tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25°C).
4. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
5. I/O Setup/Hold Slew Rate Derating
6. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
7. Maximum burst refresh cycle : 8
This derating table is used to increase t
This derating table is used to increase t
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall
tAC(max) value is measured at the low Vdd(1.7V) and hot temperature(85°C).
tAC is measured in the device with half driver strength and under the AC output load condition (Fig.7 in next Page).
Rate =-0.25ns/V.
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
Input Setup/Hold Slew Rate
I/O Setup/Hold Slew Rate
Delta Rise/Fall Rate
(V/ns)
(V/ns)
(ns/V)
±0.25
±0.5
1.0
0.8
0.6
1.0
0.8
0.6
0
DS
IS
/t
/t
IH
DH
in the case where the input slew rate is below 1.0V/ns.
in the case where the I/O slew rate is below 1.0V/ns.
+100
∆tDS
∆tDS
+100
+150
∆tIS
(ps)
+50
(ps)
+75
(ps)
+50
0
0
0
Mobile-DDR SDRAM
∆tDH
+100
∆tDH
+150
+100
∆tIH
(ps)
+50
(ps)
+50
(ps)
+75
0
0
0
February 2006