mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet

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... MFR4300 Data Sheet FlexRay Communication Controllers MFR4300 Rev. 3 04/2007 freescale.com ...

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... MFR4300 Data Sheet MFR4300 Rev. 3 04/2007 ...

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... Removed glitch from RESET# waveform. A-9: Changed maximum value of V PORD A-11: Changed “POR release level” to “POR deassert level”. A-11: Changed “V ” to “V ”. PORR PORD A-11, A.3.1.1, A.3.1.2, A.3.1.2, Table Figure Table A-1. MFR4300 Data Sheet, Rev. 3 from 2.05 to 2.07. A-12: Updated to remove B-1, Figure B-2, and Figure B-3 Freescale Semiconductor Page Number(s) N/A N ...

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... Freescale Semiconductor FlexRay Module (FLEXRAYV2) Port Integration Module (PIM) Dual Output Voltage Regulator (VREG3V3V2) Clocks and Reset Generator (CRG) Printed Circuit Board Layout Recommendations MFR4300 Data Sheet, Rev. 3 Introduction Device Overview Oscillator (OSCV2) Electrical Characteristics Package Information Index of Registers 5 ...

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... MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.2 Additional Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4 Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.1 MFR4300 Implementation Parameters and Constraints . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3.2 Part ID and Module Version Number Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.1 System Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.2 Pin Functions and Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2 ...

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... FlexRay Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 3.5.2 Number of Usable Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 3.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 3.6.1 Shut Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 3.6.2 Protocol Control Command Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 3.6.3 Protocol Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 4.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 8 Title Chapter 4 Port Integration Module (PIM) MFR4300 Data Sheet, Rev. 3 Page Freescale Semiconductor ...

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... Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Clocks and Reset Generator (CRG) 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.2 MFR4300 Relevant Pins for the CRG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 6.3 CRG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 6.3.1 Detection Enable Register (DER 222 6.3.2 Clock and Reset Status Register (CRSR 223 6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 6.4.1 Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 ...

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... A.2.3 Output Loads 248 A.3 Reset and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 A.3.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 A.3.2 Oscillator 250 A.4 Asynchronous Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 A.5 HCS12 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 10 Title Chapter 7 Oscillator (OSCV2) — OSC Operating Voltage, OSC Ground . . . . . . . . . . . . . . . . . . 233 Appendix A Electrical Characteristics MFR4300 Data Sheet, Rev. 3 Page Freescale Semiconductor ...

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... Section Number B.1 64-pin LQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Printed Circuit Board Layout Recommendations Freescale Semiconductor Title Appendix B Package Information Appendix C Appendix D Index of Registers MFR4300 Data Sheet, Rev. 3 Page 11 ...

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... Section Number 12 Title MFR4300 Data Sheet, Rev. 3 Page Freescale Semiconductor ...

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... Figure Number Figure 1-1. Order Part Number Coding Figure 2-1. MFR4300 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 2-2. MFR4300 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 2-3. Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 2-4. External Square Wave Clock Generator Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 2-5. AMI Interface with MPC5xx and MPC55xx Families . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 2-6. AMI Interface with S12X Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 2-7. ...

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... Receive FIFO B Read Index Register (RFBRIR 115 Figure 3-54. Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR 115 Figure 3-55. Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR 116 Figure 3-56. Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR 116 14 Title MFR4300 Data Sheet, Rev. 3 Page Freescale Semiconductor ...

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... Protocol Configuration Register 24 (PCR24 126 Figure 3-87. Protocol Configuration Register 25 (PCR25 127 Figure 3-88. Protocol Configuration Register 26 (PCR26 127 Figure 3-89. Protocol Configuration Register 27 (PCR27 127 Figure 3-90. Protocol Configuration Register 28 (PCR28 127 Figure 3-91. Protocol Configuration Register 29 (PCR29 128 Freescale Semiconductor Title MFR4300 Data Sheet, Rev. 3 Page 15 ...

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... Figure 3-123. Double Transmit Message Buffer State Diagram (Commit Side 170 Figure 3-124. Double Transmit Message Buffer State Diagram (Transmit Side 171 Figure 3-125. Internal Message Transfer in Streaming Commit Mode . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 3-126. Internal Message Transfer in Immediate Commit Mode . . . . . . . . . . . . . . . . . . . . . . . . 175 16 Title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 MFR4300 Data Sheet, Rev. 3 Page Freescale Semiconductor ...

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... Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Figure 6-5. Clock Monitor Failure Reset 226 Figure 6-6. External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Figure 6-7. Interface Selection during Power-on or Low Voltage Reset or Clock Monitor Failure. 227 Figure 6-8. Interface Selection during External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Freescale Semiconductor Title MFR4300 Data Sheet, Rev. 3 Page 17 ...

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... LQFP Mechanical Dimensions (Case N 840F-02) (Page 255 Figure B-2. 64-pin LQFP Mechanical Dimensions (Case N 840F-02) (Page 256 Figure B-3. 64-pin LQFP Mechanical Dimensions (Case N 840F-02) (Page 257 Figure C-1. Recommended PCB Layout (64-pin LQFP) for Standard Pierce Oscillator Mode . . . . 260 18 Title MFR4300 Data Sheet, Rev. 3 Page Freescale Semiconductor ...

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... Table Number Table 1-1. Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 1-2. Notational Conventions Table 2-1. MFR4300 Device Memory Map After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 2-2. Part ID and Module Version Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 2-3. Pin Functions and Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 2-4. MFR4300 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 2-5. CLKOUT Frequency Selection Table 2-6. Interface Selection Table 2-7 ...

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... Table 3-51. Mapping Between SSSRn and SSRn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 3-52. SSCCR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 3-53. Mapping between internal SSCCRn and SSCRn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 3-54. SSR0–SSR7 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 3-55. SSCR0–SSCR3 Field Descriptions 111 Table 3-56. MTSACFR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 20 Title MFR4300 Data Sheet, Rev. 3 Page Freescale Semiconductor ...

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... Table 3-87. Frame Data Write Access Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 3-88. Frame Data Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 3-89. Individual Message Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 3-90. Single Transmit Message Buffer Access Regions Description 153 Table 3-91. Single Transmit Message Buffer State Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Freescale Semiconductor Title MFR4300 Data Sheet, Rev. 3 Page 21 ...

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... Table 4-9. PLPPCR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 5-1. VREG3V3V2 — Signal Properties 217 Table 5-2. VREG3V3V2 — Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Table 6-1. MFR4300 Relevant Pins for the CRG 222 Table 6-2. DER Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Table 6-3. CRSR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Table 6-4. CRG Reset Sources Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 ...

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... Table A-11. Startup Characteristics 249 Table A-12. Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Table A-13. AMI Interface AC Switching Characteristics Over the Operating Range . . . . . . . . . . . . 252 Table A-14. HCS12 Interface AC Switching Characteristics Over the Operating Range . . . . . . . . . . 254 Table C-1. Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Freescale Semiconductor Title MFR4300 Data Sheet, Rev. 3 Page 23 ...

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... Table Number 24 Title MFR4300 Data Sheet, Rev. 3 Page Freescale Semiconductor ...

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... Controller Module. 1.1 Audience This data sheet is intended for application and system hardware developers who wish to develop products for the FlexRay MFR4300 assumed that the reader understands FlexRay protocol functionality and microcontroller system design. 1.2 Additional Reading For additional reading that provides background to, or supplements, the information in this manual: • ...

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... MTS Media Access Test Symbol NIT Network Idle Time PE Protocol Engine PHY Physical Layer Interface PL Physical Layer POC Protocol Operation Control SEQ Sequencer Engine Rx Reception TCU Time Control Unit Tx Transmission 26 Table 1-1. Acronyms and Abbreviations Meaning MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Table 1-2. Notational Conventions Speed Option MHz Package Option AE = 64-pin Lead Free / Halide Free LQFP Temperature Option M = -40 Device Title Controller Family Qualification P = Engineering Sample M = Qualified part Figure 1-1. Order Part Number Coding MFR4300 Data Sheet, Rev. 3 Introduction +125 C 27 ...

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... Introduction 28 MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Device Overview 2.1 Introduction The MFR4300 FlexRay Communication Controller implements the FlexRay protocol according to the FlexRay Communications System Protocol Specification V2.1. The controller host interface (CHI) of the MFR4300 FlexRay Communication Controller is implemented in accordance with Chapter 3, “FlexRay Module (FLEXRAYV2)” 2.2 Features The MFR4300 FlexRay controller provides the following features: • ...

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... One absolute timer • One timer that can be configured to absolute or relative Features specific to the MFR4300 include the following: • Two hardware selectable host interfaces: — HCS12 Interface for direct connection to Freescale’s HCS12 family of microcontrollers, with interface clock signal to synchronize the data transfer (the maximum frequency of this clock ...

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... Implementation Constraints • The external clock frequency for EXTAL/CLK_CC is 40 MHz. • The minimum external clock frequency for CHICLK_CC (when selected MHz. • The maximum external clock frequency for CHICLK_CC is 80 MHz Freescale Semiconductor MFR4300 Data Sheet, Rev. 3 Device Overview 31 ...

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... A8 A9 OE#/ACS0 A11/ACS1 A12/ACS2 WE#/RW_CC# CE#/LSTRB A10/ECLK_CC INT_CC# BSEL0#/DBG1 BSEL1#/DBG0 RXD_BG1 TXD_BG1/IF_SEL1 TXEN1# TEST Figure 2-1. MFR4300 Functional Block Diagram 32 Voltage Regulator Clock and Reset Gen. Module Oscillator External Clock Interface HCS12 AMI Interface External Bus Interface Receiver A Receiver B Transmitter A ...

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... For detailed information on the MFR4300 FlexRay module registers, see 2 For detailed information on the MFR4300 CRG module registers, see 3 For detailed information on the MFR4300 PIM module registers, see Freescale Semiconductor Registers Chapter 3, “FlexRay Module Chapter 6, “Clocks and Reset Generator Chapter 4, “Port Integration Module MFR4300 Data Sheet, Rev ...

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... These read-only values provide a unique ID for each revision of the device. 2.4 Signal Descriptions 2.4.1 System Pinout The MFR4300 is available in a 64-pin low profile quad flat package (LQFP). Most pins perform two functions, as described in Section 2.4.2, “Pin Functions and Signal assignments. For a recommended printed circuit board layout, see ...

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... D12/PB3 5 D13/PB2 6 D14/PB1 7 VDDX1 8 VSSX1 9 D15/PB0 10 A1/XADDR19 11 A2/XADDR18 12 A3/XADDR17 13 A4/XADDR16 14 A5/XADDR15 15 RESET# 16 Freescale Semiconductor Figure 2-2. MFR4300 Pin Assignment MFR4300 Data Sheet, Rev. 3 Device Overview BSEL1#/DBG0 48 BSEL0#/DBG1 47 DBG3/CLK_S1 46 45 TXD_BG2/IF_SEL0 44 TXEN2# RXD_BG2 43 42 DBG2/CLK_S0 41 TXD_BG1/IF_SEL1 40 D1/PA6 D0/PA7 39 VSSX2 38 37 VDDX2 ...

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... AMI data bus / HCS12 multiplexed address/data bus I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus MFR4300 Data Sheet, Rev. 3 Functional Description Freescale Semiconductor ...

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... Factory Test mode select – must be tied to logic low in application I/O DC/PD - Debug strobe point / Output clock select I/O DC/PD - Debug strobe point / Output clock select Oscillator Crystal driver / External clock - Crystal driver Supply/Bypass Filter pins - - - - Supply voltage, I/O MFR4300 Data Sheet, Rev. 3 Device Overview Functional Description 37 ...

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... Core voltage power supply output (nominally 2.5V Core voltage ground output - - - - Oscillator voltage power supply output (nominally 2.5V Oscillator voltage ground output (HIPPER)” (HIPPCR)” (HIPDSR)” (PLPDSR)” MFR4300 Data Sheet, Rev. 3 Functional Description (PLPPER)” (PLPPCR)” Freescale Semiconductor ...

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... Interface” for more information. The pin can be configured to enable or disable either a pullup or pulldown resistor on the pin. OE# is the AMI interface output enable signal. This signal controls MFR4300 data output and the state of three-stated data pins D[15:0] during host read operations. ACS0 is an HCS12 interface address select signal. ...

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... Interface” for more information. The pin can be configured to enable or disable either a pullup or pulldown resistor on the pin. WE AMI interface write select signal. It strobes the valid data provided by the host on the D[15:0] pins during write operations to the MFR4300 memory. 40 Section 3.4.16, “Strobe Signal Support” ...

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... The IF_SEL[1:0] signals are inputs during the internal reset sequence and are latched during the internal reset sequence. Freescale Semiconductor Section 2.7, “External Host and t LEC HEC NOTE MFR4300 Data Sheet, Rev. 3 Device Overview Interface” given in Table A-14.) Table 2-6 for the selection ...

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... The pin can be configured to provide either high or reduced output drive. This is an open-drain output. 2.4.3.18 TEST The TEST pin is pulled down, internally, and must be tied to VSS in all applications. 42 Selection”). NOTE Control” for more MFR4300 Data Sheet, Rev. 3 Values”. Freescale Semiconductor ...

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... C2 • • See crystal manufacturer’s product specification for recommended values Oscillator supply output capacitor C3 = 220 nF C3 VSSOSC Figure 2-3. Oscillator Connections MFR4300 Data Sheet, Rev. 3 Device Overview for more information. Figure 2-3 for Pierce oscillator Chapter 7, “Oscillator (OSCV2)”. Figure 2-4 for external ...

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... Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MFR4300 as possible. Bypass requirements depend on how heavily the MFR4300 pins are loaded. Table 2-4. MFR4300 Power and Ground Connection Summary ...

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... VDD2_5, VSS2_5 — Core Power Pins Power is supplied to the MFR4300 core through VDD2_5 and VSS2_5. This 2.5 V supply is derived from the internal voltage regulator. No static load is allowed on these pins. If VDDR is tied to ground, the internal voltage regulator is turned off. ...

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... As the CLK_S[1:0] signals are multiplexed with DBG[2:3], CLKOUT should be selected using pullup and pulldown resistors 2.6.2 External Host Interface Selection The MFR4300 can be connected and controlled by two types of interface through the CC EBI. Two pins, IF_SEL0 and IF_SEL1, are used to configure the interface type, in accordance with Pin IF_SEL0 ...

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... The listed values are calculated for the MFR4300-Physical Layer connection where no internal pullup/pulldown resistors are assumed in the Electrical PHY at the TXD_BG1 and TXD_BG2 interface lines Electrical PHY device has internal pullup/pulldown resistors connected to these signals, then the external pullup/pulldown resistor ...

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... Illegal access 16-bit read from word address access NOTE NOTE MFR4300 Data Sheet, Rev. 3 Type of Access Freescale Semiconductor ...

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... MPC55xx Family … DATA15 ADDR19 … ADDR30 BE0 BE1 WE# CSn# OE# IRQn# Figure 2-5. AMI Interface with MPC5xx and MPC55xx Families Freescale Semiconductor VDDXn PL Interface VSSXn MFR4300 Data Sheet, Rev. 3 Device Overview MFR4300 D15 … D0 A12 … A1 BSEL1# BSEL0# WE# CE# OE# INT_CC# TXD_BG2/IF_SEL0 TXD_BG1/IF_SEL1 ...

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... Asynchronous Memory Interface with S12X Family S12X Family D15 … D0 A12 … A1 UDS LDS CSn WE RE IRQn 50 VDDXn PL Interface VSSXn Figure 2-6. AMI Interface with S12X Family MFR4300 Data Sheet, Rev. 3 MFR4300 D15 … D0 A12 … A1 BSEL1# BSEL0# CE# WE# OE# INT_CC# TXD_BG2/IF_SEL0 TXD_BG1/IF_SEL1 Freescale Semiconductor ...

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... PA6 with ACS1, PA7 with ACS2. The address decoding phase of a read/write operation is passed if all the comparisons described above are passed. Freescale Semiconductor VDDXn PL Interface VSSXn Timing” for timing characteristics of the CC AMI NOTE MFR4300 Data Sheet, Rev. 3 Device Overview MFR4300 D15 … D0 A12 … A1 ...

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... Not supported 16-bit read from an even address Not supported Not supported Not supported MFR4300 Data Sheet, Rev. 3 Type of Access Freescale Semiconductor ...

Page 53

... DATA SIGNALS ADR[0:15] 16 bit ADDRESS SIGNALS ADR[0:9] 10 bit ADDRESS SIGNALS Address ADR[13:15] Comparator 1 3 bit ACS[0:2] 3 bit Address XADDR[14:19] Comparator 2 6 bit ‘000000’ 6 bit 1 ADR[14:15] 2 bit ‘01’ 2 bit Address Comparator 3 MFR4300 Data Sheet, Rev. 3 Device Overview & ...

Page 54

... ADDR/DATA15 (PA7) … ADDR/DATA0 (PB0) XADDR19 … XADDR14 ECLK LSTRB R/W# IRQn# Figure 2-9. HCS12 interface with HCS12 Page Mode Support 54 VDDXn PL Interface VSSXn MFR4300 Data Sheet, Rev. 3 MFR4300 PA7 … PB0 XADDR19 … XADDR14 ECLK_CC LSTRB RW_CC# ACS2 ACS1 ACS0 INT_CC# TXD_BG1/IF_SEL1 ...

Page 55

... Figure 2-10. HCS12 interface with HCS12 Unpaged Mode Support 2.7.2.3 HCS12 Interface Timing See Section A.5, “HCS12 Interface 2.8 Resets and Interrupts 2.8.1 Resets MFR4300 has the following resets: • External hard reset input signal RESET#. Freescale Semiconductor 6 VSSXn VDDXn PL Interface VSSXn Timing” for timing characteristics of the HCS12 interface. ...

Page 56

... Internal clock monitor failure reset (see When a reset occurs, MFR4300 registers and control bits are changed to known startup states. Refer to the respective module chapters for information on the different kinds of resets and for register reset states. 2.8.1.1 I/O Pin States After Reset ...

Page 57

... Message Buffer Number: Position of message buffer configuration registers within the register map. For example, Message Buffer Number 5 corresponds to the MBCCS5 register. MCU Microcontroller Unit PT Microtick MT Macrotick MTS Media Access Test Symbol Freescale Semiconductor Table 3-1. List of Terms (Sheet Definition MFR4300 Data Sheet, Rev ...

Page 58

... Clock domain crossing unit (CDC) A block diagram of the FlexRay module with its surrounding modules is given in 58 Table 3-1. List of Terms (Sheet Definition green italics. An example is the state MFR4300 Data Sheet, Rev. 3 POC:state blue italics. An example is the POC:normal active. Figure 3-1. Freescale Semiconductor ...

Page 59

... The FlexRay module provides the following features: Freescale Semiconductor FlexRay Module CHI config HIF SEARCH LUT BCU MIF Figure 3-1. FlexRay Module Block Diagram NOTE MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) RXD_BG1 PE TXD_BG1 SEQ TXEN1# RXD_BG2 TxA TXD_BG2 TXEN2# RxA DBG0 ...

Page 60

... ID filtering for the dynamic segment • 4 configurable slot error counters • 4 dedicated slot status indicators — used to observe slots without using receive message buffers • measured value indicators for the clock synchronization 60 MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 61

... For details regarding protocol states, see FlexRay Communications System Protocol Specification, Version 2.1. Freescale Semiconductor Descriptions”. (MCR). The FlexRay module then deasserts the protocol engine reset POC:default config state. NOTE (MCR). POC:default config MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Module Configuration state. Module Configuration Register Protocol Operation (MCR), 61 ...

Page 62

... Low 1 — 0 — 0 — 0 — 0 MFR4300 Data Sheet, Rev. 3 Descriptions”. Function Receive Data Channel A Transmit Data Channel A Transmit Enable Channel A Receive Data Channel B Transmit Data Channel B Transmit Enable Channel B Debug Strobe Signal 0 Debug Strobe Signal 1 Debug Strobe Signal 2 Debug Strobe Signal 3 ...

Page 63

... Global Interrupt Flag and Enable Register (GIFER) Protocol Interrupt Flag Register 0 (PIFR0) Protocol Interrupt Flag Register 1 (PIFR1) Protocol Interrupt Enable Register 0 (PIER0) Protocol Interrupt Enable Register 1 (PIER1) CHI Error Flag Register (CHIERFR) Message Buffer Interrupt Vector Register (MBIVEC) MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Table 3-3. Access R R/W ...

Page 64

... Timer Configuration and Control Register (TICCR) Timer 1 Cycle Set Register (TI1CYSR) Timer 1 Macrotick Offset Register (TI1MTOR) Timer 2 Configuration Register 0 (TI2CR0) Timer 2 Configuration Register 1 (TI2CR1) Slot Status Configuration Slot Status Selection Register (SSSR) Slot Status Counter Condition Register (SSCCR) MFR4300 Data Sheet, Rev. 3 Access R/W ...

Page 65

... Receive FIFO - Status Receive FIFO A Read Index Register (RFARIR) Receive FIFO B Read Index Register (RFBRIR) Receive FIFO - Filter Dynamic Segment Status Protocol Configuration Protocol Configuration Register 0 (PCR0) ... Protocol Configuration Register 30 (PCR30) MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Access ...

Page 66

... Message Buffers Configuration, Control, Status Message Buffer Frame ID Register 0 (MBFIDR0) Message Buffer Index Register 0 (MBIDXR0) ... Message Buffer Frame ID Register 127 (MBFIDR127) Message Buffer Index Register 127 (MBIDXR127) Table 3-4. Register Access Conventions Description Message Buffer Index Registers (MBIDXRn) MFR4300 Data Sheet, Rev. 3 Access R R/W R/W R/W R/W ... R/W ...

Page 67

... Write access only when the FlexRay module is in Normal Mode. POC:config Write access only when the Protocol is in the Write access only when the related Message Buffer is disabled. Write access only when the related Message Buffer is locked. MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Description (POCR). Table 3-6 ...

Page 68

... Figure 3-2. Module Version Register (MVR) Table 3-7. MVR Field Descriptions Description CHA SFFE MFR4300 Data Sheet, Rev PEVER Write: MEN, SCM, CHB, CHA: Disabled Mode SFFE: Disabled Mode or POC:config ...

Page 69

... RXD_BG2, TXD_BG2, and TXEN1# driven by FlexRay module channel 0 active PE channel 1 active Freescale Semiconductor Table 3-8. MCR Field Descriptions Description Modes”. pChannels Filtering”. Description Dual Channel Device Modes Single Channel Device Mode MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Section 3.1.6, 69 ...

Page 70

... Description Figure 3-132) 16-bit write access required SEL NOTE Description MFR4300 Data Sheet, Rev. 3 Write: Any Time ENB STBPSEL Table 3-11 Section 3.4.16, “Strobe ...

Page 71

... Freescale Semiconductor Description Description Channel MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) 1 Type Offset Reference - value 0 MT start A RXD_BG1 level +5 B RXD_BG2 A RXD_BG1 value ...

Page 72

... Description Channel 2 MFR4300 Data Sheet, Rev Type Offset Reference A RXD_BG1 pulse +5 B RXD_BG2 A RXD_BG1 level +4 B RXD_BG2 A RXD_BG1 pulse +4 B RXD_BG2 ...

Page 73

... STB2EN 0 Strobe port DBG2 disabled 1 Strobe port DBG2 enabled Freescale Semiconductor Description Table 3-12. STBPCR Field Descriptions Description MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) 1 Channel Type Offset B value 0 - pulse 0 A pulse pulse 0 - value +1 ...

Page 74

... Description Table 3-13. MBDSR Field Descriptions Description MFR4300 Data Sheet, Rev. 3 Write: POC:config MBSEG1DS Write: POC:config LAST_MB_UTIL ...

Page 75

... Table 3-14. MBSSUTR Field Descriptions Description BSY EOC_AP ERC_AP WMC Section 3.4.11, “External Clock Description Protocol Configuration Register 29 MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: Normal Mode POCCMD Execution”. Synchronization”. (PCR29). 1 ...

Page 76

... POC:config state. POC:halt state. POC:startup start state. POC:default config POC:halt state NOTE RESET command mandatory to execute the Section 3.6.3, “Protocol Reset Command” MFR4300 Data Sheet, Rev. 3 (CHIERFR), and will not change the value POC:ready state. state. Freescale Semiconductor ...

Page 77

... Description and Protocol Interrupt Flag Register 1 (PIFR1) is asserted and the chi error interrupt enable GIFER.CHIE is asserted. The FlexRay Protocol Status Register 3 (PSR3). Receive FIFO B Read Index Register (RFBRIR) MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: Normal Mode ...

Page 78

... FNEAIF flag is set. 0 Disable interrupt line 1 Enable interrupt line 78 Description Receive FIFO A Read Index Register (RFARIR) MFR4300 Data Sheet, Rev. 3 and clears the interrupt flag if the are asserted. The application can not are equal to ‘1’. The Freescale Semiconductor ...

Page 79

... Description POC:halt POC:halt when the CONFIG_COMPLETE command was sent Protocol Operation Control Register MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: Normal Mode state immediately. The fatal protocol errors are: state immediately. An internal protocol ...

Page 80

... FSP process of the FlexRay protocol such event. 1 Transmission across boundary violation occurred on channel B. 80 Description Protocol Configuration Register 0 and the rate_correction_out field in the (PCR14). (PCR30). MFR4300 Data Sheet, Rev. 3 (PCR0). Protocol Protocol pLatestTx violation, as pLatestTx violation as Freescale Semiconductor ...

Page 81

... Protocol Engine Communication Failure detected. Freescale Semiconductor Description Description is changed by the FlexRay module. Section 3.6.2, “Protocol Control Command MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: Normal Mode Protocol Operation Control Register Execution” ...

Page 82

... Description has changed. Slot Status Counter Registers (SSCR0–SSCR3 Protocol Interrupt Flag Register 0 (PIFR0) Table 3-19. PIER0 Field Descriptions Description MFR4300 Data Sheet, Rev incremented. Write: Any Time Freescale Semiconductor ...

Page 83

... R W Reset Figure 3-13. Protocol Interrupt Enable Register 1 (PIER1) Freescale Semiconductor Description MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: Any Time ...

Page 84

... CHI interrupt enable bit CHIE in the Register (GIFER). 84 Protocol Interrupt Flag Register 1 (PIFR1) Table 3-20. PIER1 Field Descriptions Description MFR4300 Data Sheet, Rev. 3 Write: Normal Mode Global Interrupt Flag and Enable Freescale Semiconductor can 1 0 ...

Page 85

... No such event 1 Double transmit buffer lock error occurred Freescale Semiconductor Description Protocol Operation Control Register (POCR) (MBSSUTR). MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) while the BSY flag is equal Message Buffer CHI Error Flag Register 85 ...

Page 86

... Figure 3-15. Message Buffer Interrupt Vector Register (MBIVEC) 86 Description Protocol Configuration Register 24 Protocol Configuration Register 19 Network Management Vector Length Register Network Management Vector Registers MFR4300 Data Sheet, Rev. 3 (PCR24). (PCR19). (NMVR0–NMVR5)) are not RBIVEC Freescale Semiconductor (NMVLR). 1 ...

Page 87

... STATUS_ERR_CNT vSS!SyntaxError, vSS!ContentError, Section 3.4.18, “Slot Status Table 3-23. CASERCR Field Descriptions Description Additional Reset: RUN Command STATUS_ERR_CNT MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2 vSS!BViolation, Monitoring” ...

Page 88

... POC:startup 88 Section 3.4.18, “Slot Status Table 3-24. CBSERCR Field Descriptions Description PROTSTATE STARTUPSTATE Description vPOC!State. This field indicates the state of the protocol. MFR4300 Data Sheet, Rev. 3 Monitoring” WAKEUPSTATUS Freescale Semiconductor ...

Page 89

... Figure 3-19. Protocol Status Register 1 (PSR1) Freescale Semiconductor Description vPOC!StartupState REMCSAT CPN HHR MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) This field indicates the current sub-state of the Write: Normal Mode FRZ APTAC ...

Page 90

... Additional Reset: RUN Command MFR4300 Data Sheet, Rev. 3 POC:normal active vRemainingColdstartAttempts vPOC!ColdstartNoise POC:normal active state via the leading cold start state via noisy leading cold start path POC:halt state due to the host FREEZE POC:default config state. ...

Page 91

... This status bit is set when a syntax error was detected during NIT on channel such event 1 Syntax error detected Freescale Semiconductor Description vSS!BViolation vSS!SyntaxError vSS!BViolation vSS!SyntaxError MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) for NIT on channel B for NIT on channel B vSS!TxConflict for symbol vSS!BViolation for symbol vSS!SyntaxError ...

Page 92

... Description Protocol Configuration Register 8 Additional Reset: RUN Command MFR4300 Data Sheet, Rev. 3 vSS!TxConflict for symbol vSS!BViolation for symbol vSS!SyntaxError for symbol window vSS!ValidMTS vClockCorrectionFailed (PCR8). The POC:normal active Write: Normal Mode ...

Page 93

... Aggregated Content Error on Channel A — This flag is set when a content error has been detected on ACEA channel A. Content errors are detected in the communication slots, the symbol window, and the NIT content error detected 1 Content error detected Freescale Semiconductor Description MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) 93 ...

Page 94

... MTCT Table 3-29. MTCTR Field Descriptions Description vMacrotick Table 3-30. CYCTR Field Descriptions Description vCycleCounter MFR4300 Data Sheet, Rev CYCCNT Freescale Semiconductor ...

Page 95

... Description Table 3-32. SLTCTBR Field Descriptions Description Additional Reset: RUN Command RATECORR MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2 SLOTCNTA vSlotCounter for channel SLOTCNTB ...

Page 96

... MIF PRIF CHIF MFR4300 Data Sheet, Rev. 3 (before value limitation and external rate Protocol Configuration Register 13 Protocol Interrupt Flag Register (before value limitation and external Protocol Configuration Register Protocol Interrupt Flag ...

Page 97

... Table 3-35. CIFRR Field Descriptions Description or Protocol Interrupt Flag Register 1 (PIFR1) is equal equal equal to 1. MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) and are provided here to simplify the Global Interrupt Flag and is equal to 1. CHI Error Flag Message Buffer Configuration, ...

Page 98

... NOTE Table 3-36. SFCNTR Field Descriptions Description SFT_OFFSET[15: Tables”. MFR4300 Data Sheet, Rev SFODB SFODA (vsSyncIdListB for even cycle) (vsSyncIdListA for even cycle) (vsSyncIdListB for odd cycle) (vsSyncIdListA for odd cycle) ...

Page 99

... Tables are not valid (update is ongoing) 1 Tables are valid (consistent). Freescale Semiconductor Table 3-37. SFTOR Field Description Description CYCNUM ELKS OLKS EVAL OVAL Tables”. Description MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: Normal Mode OPT ...

Page 100

... For details see 100 Description 16-bit write access required Table 3-39. SFIDRFR Field Descriptions Description Section 3.4.15.2, “Sync Frame Rejection MFR4300 Data Sheet, Rev. 3 Write: Normal Mode SYNFRID Filtering”. Freescale Semiconductor ...

Page 101

... Table 3-41. SFIDAFMR Field Descriptions Description Network Management Vector Length Register MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: POC:config FVAL Section 3.4.15, Write: POC:config FMSK 0 ...

Page 102

... Table 3-42. NMVR[0:5] Field Descriptions Description NMVn Received Payload ... Table 3-44. NMVLR Field Descriptions Description MFR4300 Data Sheet, Rev. 3 Network Management Vector Registers Table NMV0 NMV1 NMV2 NMV3 NMV10 NMV11 Write: POC:config NMVL 0 ...

Page 103

... Write: T2_REP, T1_REP, T1SP, T2SP, T1TR, T2TR: Normal Mode T2ST 0 T2SP T2TR Table 3-45. TICCR Field Descriptions Description NOTE or POC:normal MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: T2_CFG: POC:config T1_ REP T1SP T1TR Section 3.4.17, passive ...

Page 104

... T1”. Table 3-46. TI1CYSR Field Descriptions Description NOTE T1_MTOFFSET T1”. Table 3-47. TI1MTOR Field Descriptions Description NOTE MFR4300 Data Sheet, Rev. 3 Write: Any Time T1_CYC_MSK Write: Any Time ...

Page 105

... T2_CYC_VAL T2_MTCNT[31:16 Table 3-48. TI2CR0 Field Descriptions Description Fields for absolute timer T2 (TICCR.T2_CFG = ‘0’) Fields for relative timer T2 (TICCR.T2_CFG = ‘1’) NOTE MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: Any Time T2_CYC_MSK Timer Configuration and Control Section 3.4.17.2, “ ...

Page 106

... Fields for absolute timer T2 (TICCR.T2_CFG = ‘0’) Fields for relative timer T2 (TICCR.T2_CFG = ‘1’) NOTE 16-bit write access required MFR4300 Data Sheet, Rev. 3 Write: Any Time Timer Configuration and Control Section 3.4.17.2, “Absolute / Relative Write: Any Time ...

Page 107

... CNTCFG MCY VFR Section 3.4.18.4, “Slot Status Counter MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Table 3-51. For a detailed Monitoring”. Odd Communication Cycle For Channel B For Channel SSR1[15:8] SSR1[7:0] SSR3[15:8] SSR3[7:0] SSR5[15:8] SSR5[7:0] ...

Page 108

... STATUSMASK[0] – This bit enables the counting for slots with the transmission conflict indicator bit set to ‘1’. Table 3-53. Mapping between internal SSCCRn and SSCRn Condition Register 108 Table 3-52. SSCCR Field Descriptions Description Condition Defined for Register SSCCR0 SSCR0 SSCCR1 SSCR1 SSCCR2 SSCR2 SSCCR3 SSCR3 MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 109

... Table 3-54. SSR0–SSR7 Field Descriptions Description vSS!ValidFrame = ‘0’ = ‘1’ = ‘0’ = ‘1’ = ‘0’ = ‘1’ vSS!SyntaxError vSS!ContentError vSS!ValidFrame = ‘0’ = ‘1’ MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2 SYA NFA SUA SEA CEA ...

Page 110

... Description = ‘0’ = ‘1’ = ‘0’ = ‘1’ vSS!SyntaxError vSS!ContentError SLOTSTATUSCNT Section 3.4.18.4, “Slot Status Counter NOTE MFR4300 Data Sheet, Rev. 3 vRF!Header!NFIndicator channel A vRF!Header!SuFIndicator channel A channel A channel A vSS!BViolation channel A vSS!TxConflict channel Slot Status Counter Registers” ...

Page 111

... Generation”. Table 3-56. MTSACFR Field Descriptions Description CYCCNTMSK Generation”. MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: CYCCNTMSK, CYCCNTVAL: POC:config Write: MTE: Any Time CYCCNTVAL Write: CYCCNTMSK, CYCCNTVAL: POC:config ...

Page 112

... Table 3-57. MTSBCFR Field Descriptions Description 16-bit write access required Concept”. Table 3-58. RSBIR Field Descriptions Description MFR4300 Data Sheet, Rev. 3 Write: WMD, SEL: Any Time Write: RSBIDX: POC:config RSBIDX Freescale Semiconductor ...

Page 113

... Table 3-59. Register Table 3-60. RFSR Field Descriptions Description MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: Any Time Write: POC:config SIDX ...

Page 114

... Table 3-62. RFDSR Field Descriptions Description Table 3-63. RFARIR Field Descriptions Description Global Interrupt Flag and Enable Register MFR4300 Data Sheet, Rev. 3 Write: POC:config ENTRY_SIZE RDIDX ...

Page 115

... Table 3-64. RFBRIR Field Descriptions Description (GIFER).The index wraps back to the first message buffer NOTE MIDAFVAL Section 3.4.9.5, “Receive FIFO MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2 RDIDX Write: POC:config ...

Page 116

... Section 3.4.9.5, “Receive FIFO Table 3-66. RFMIAFMR Field Descriptions Description Section 3.4.9.5, “Receive FIFO Table 3-67. RFFIDRFVR Field Descriptions Description MFR4300 Data Sheet, Rev. 3 Write: POC:config filtering”. Write: POC:config FIDRFVAL ...

Page 117

... Table 3-68. RFFIDRFMR Field Descriptions Description 16-bit write access required Section 3.4.9.5, “Receive FIFO Table 3-69. RFRFCFR Field Descriptions Description MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: POC:config FIDRFMSK filtering”. Write: WMD, IBD, SEL: Any Time ...

Page 118

... F3MD F2MD F1MD F0MD Table 3-70. RFRFCTR Field Descriptions Description MFR4300 Data Sheet, Rev. 3 Write: Any Time F3EN F2EN F1EN F0EN LASTDYNTXSLOTA ...

Page 119

... Table 3-72. LDTXSLBR Field Descriptions Description Table 1 Description gColdstartAttempts gdActionPointOffset - 1 gdCASRxLowMax - 1 gdDynamicSlotIdlePhase gdMinislotActionPointOffset - 1 gdMinislot - gdMinislotActionPointOffset gdStaticSlot MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) zLastDynTxSlot channel zLastDynTxSlot channel B 3-73. For more details about the Min Max Unit number ...

Page 120

... MFR4300 Data Sheet, Rev. 3 Min Max Unit PCR bool - 1 MT gdBit gdBit gdBit gdBit gdBit gdBit PT 16/ cyclepairs ...

Page 121

... Table 3-74. Wakeup Channel Selection wakeup_channel Wakeup Channel macro_after_first_static_slot MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Min Max Unit bool see Table 3-74 number PT PT 0x000 0x7FF number PT PT Write: POC:config ...

Page 122

... MFR4300 Data Sheet, Rev. 3 Write: POC:config number_of_static_slots Write: POC:config coldstart_attempts Write: POC:config wakeup_symbol_rx_window 0 ...

Page 123

... MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: POC:config micro_per_macro_nom_half Write: POC:config wakeup_symbol_tx_idle Write: POC:config ...

Page 124

... MFR4300 Data Sheet, Rev. 3 Write: POC:config Write: POC:config Write: POC:config ...

Page 125

... MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: POC:config Write: POC:config noise_listen_timeout[24:16 Write: POC:config ...

Page 126

... MFR4300 Data Sheet, Rev. 3 Write: POC:config micro_initial_offset_a Write: POC:config Write: POC:config micro_per_cycle[19:16 ...

Page 127

... MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Write: POC:config Write: POC:config micro_per_cycle_max [19:16 Write: POC:config ...

Page 128

... Protocol Configuration Register 30 (PCR30 CMT MBIE EDT LCKT Description Message Buffer Configuration MFR4300 Data Sheet, Rev. 3 Write: POC:config Write: POC:config sync_node_max ...

Page 129

... Message transferred for the first time. 1 Message will be transferred again. Freescale Semiconductor Description Message Buffer Control Message Buffer Status Section 3.4.6.3.4, “Message Buffer Status Update” for a detailed update description of the update conditions. MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Update” for a detailed 129 ...

Page 130

... Cycle Counter Filtering Value — This field defines the filter value for the cycle counter filtering. CCFVAL 130 Description Section 3.4.6.3.4, “Message Buffer Status Update” CCFMSK Filtering”. Table 3-76. MBCCFRn Field Descriptions Description Table 3-77. MFR4300 Data Sheet, Rev. 3 Write: POC:config CCFVAL Freescale Semiconductor for a or MB_DIS 1 0 ...

Page 131

... Table 3-78. MBFIDRn Field Descriptions Description MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Receive Message Buffer dynamic segment store first valid frame received on channel A, ignore channel B store first valid frame received on channel B ...

Page 132

... FlexRay module updates this register after frame reception or transmission. 132 bits located in physical memory, not affected by reset Table 3-79. MBIDXRn Field Descriptions Description MFR4300 Data Sheet, Rev. 3 Write: POC:config MBIDX reset value Freescale Semiconductor or MB_DIS 1 0 ...

Page 133

... FlexRay Communications System Protocol Freescale Semiconductor Buffer”. Frame Data Message Buffer Data Field Frame Header Data Field Offset Message Buffer Header Field MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Section 3.4.3, Slot Status Figure 3-97. The physical 133 ...

Page 134

... Each individual message buffer consists of two parts, the physical message buffer, which is located in the FRM, and the message buffer control data, which are located in dedicated registers. The structure of an individual message buffer is given in 134 Description”. Equation Types”. Section 3.4.6, “Individual Message Buffer Figure 3-98. MFR4300 Data Sheet, Rev. 3 SADR_MBDF of the 3-1. Eqn. 3-1 Freescale Semiconductor ...

Page 135

... MBDSR.MBSEG[1, bytes FrameData Message Buffer Data Field Frame Header Data Field Offset Message Buffer Header Field MBCCFRn MBFIDRn Message Buffer Control Registers (MBSSUTR). All individual message buffers with MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) (MBIDXRn). Slot Status MBIDXRn Eqn. 3-2 135 ...

Page 136

... Receive Shadow Buffer Index Register >= MBDSR.MBSEG[1, bytes Frame Data Message Buffer Data Field Frame Header Data Field Offset Message Buffer Header Field RSBIDX_0 Receive Shadow Buffer Control Register MFR4300 Data Sheet, Rev. 3 3-3. (RSBIR). Slot Status RSBIDX_1 RSBIDX_2 RSBIDX_3 Freescale Semiconductor Eqn. 3-3 ...

Page 137

... Freescale Semiconductor Receive FIFO Start Index Register Receive FIFO Depth and Size Register / Receive FIFO B Read Index Register Equation 3-4. Equation 3-5. NOTE MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Figure 3-100. (RFSIR), the FIFO (RFDSR), and the read index field Eqn. 3-4 Eqn. 3-5 137 ...

Page 138

... Frame Header i Frame Header 1 Message Buffer Header Fields RFSIR RFARIR RFDSR RFARIR Receive FIFO Control Register Figure 3-100. Receive FIFO Structure MFR4300 Data Sheet, Rev. 3 Data Field Offset n Slot Status n Data Field Offset i Slot Status i Data Field Offset 1 Slot Status 1 Freescale Semiconductor ...

Page 139

... The configuration data are located in the following registers: Freescale Semiconductor Segments” Message Buffer Configuration, Control, Status Registers Receive Shadow Buffer Index Register or POC:normal passive state, the receive shadow buffers are MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) 139 ...

Page 140

... Receive FIFO B Read Index Register (RFARIR), the application must write ‘1’ to the FIFO A Not Empty the application must write ‘1’ to the FIFO B Not Empty Interrupt NOTE MFR4300 Data Sheet, Rev. 3 Receive FIFO A (RFBRIR). To update the (GIFER). To update the (GIFER). Each update increments the ...

Page 141

... Figure 3-101. Example of FRM Layout Equation 3-6. MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Data Field Offset Slot Status ...

Page 142

... The frame header will be read out when the frame is transferred to the FlexRay bus. The structure of the frame header in the message buffer header field is given in description of the frame header fields is given in 142 Tables” for the description of the sync Table 3-81. MFR4300 Data Sheet, Rev. 3 Section 3.4.2.1, “Message Buffer Figure 3-102. A detailed Freescale Semiconductor ...

Page 143

... CYCCNT Figure 3-102. Frame Header Structure TX Static Segment Commit Side Transmit Side POC:config or MB_DIS POC:config or MB_DIS Protocol Configuration Register 19 CHI Error Flag Register (CHIERFR) MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2 FID PLDLEN HDCRC Table POC:config Double Buffered Dynamic Segment ...

Page 144

... Null Frame Indicator Sync Frame Indicator Sync Frame Indicator Startup Frame Indicator (MBFIDRn). If the FlexRay module detects a mismatch (MBFIDRn). MFR4300 Data Sheet, Rev. 3 Protocol Configuration Register 24 CHI Error Flag Payload Preamble Indicator in the FlexRay frame Payload Preamble in the FlexRay frame header. ...

Page 145

... Freescale Semiconductor Description Header CRC value as it was given by the application.The Header CRC field of the transmitted frame. Section 3.4.2.1.2, “Data Field MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Payload length Header CRC of the received frame. Offset”. Table 3-82. ...

Page 146

... Description Common Message Buffer Status Bits vSS!ValidFrame = ‘0’ = ‘1’ = ‘0’ = ‘1’ = ‘0’ = ‘1’ MFR4300 Data Sheet, Rev. 3 Slot Status Content see Figure 3-103 see Figure 3-104 see Figure 3-105 see Figure 3-104 see ...

Page 147

... Table 3-84. MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) channel B channel B channel B channel A channel A channel A vRF!Header!SuFIndicator channel A channel A channel A channel A 147 ...

Page 148

... Description vSS!ValidFrame = ‘0’ = ‘1’ = ‘0’ = ‘1’ = ‘0’ = ‘1’ vSS!SyntaxError vSS!ContentError MFR4300 Data Sheet, Rev. 3 Slot Status Content see Figure 3-106 see Figure 3-107 see Figure 3-108 Table 3-83 SYA ...

Page 149

... Figure 3-109. minimum length defined by MBDSR.MBSEG1DS MBDSR.MBSEG1DS MBDSR.MBSEG2DS MBDSR.MBSEG2DS RFDSR.ENTRY_SIZE (RFSR.SEL = 0) MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) channel B vSS!TxConflict channel B channel A channel A channel A vRF!Header!SuFIndicator channel A channel A channel A channel A vSS!TxConflict channel A Table 3-86 ...

Page 150

... Table 3-86 ... Message Buffer Index Registers Receive FIFO B Read Index Register (RFBRIR) Receive FIFO A Read Index Register (RFARIR) (RFBRIR). MFR4300 Data Sheet, Rev DATA1 / MID1 / NMV1 DATA3 / NMV3 ... DATA N-1 (MBIDXRn). While the message Receive FIFO A Read when the related receive ...

Page 151

... Segment Size and Utilization Register Freescale Semiconductor single buffered commit side or MB_DIS POC:config or MB_DIS or MB_LCK or MB_LCK Table 3-88. Frame Data Field Descriptions Description (MBSSUTR). MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) double buffered transmit side POC:config or MB_DIS Data”. POC:config state. Message Buffer 151 ...

Page 152

... Individual Message Buffer Description Receive Message Buffer Single Transmit Message Buffer Double Transmit Message Buffer Message Buffer Configuration, Control, Status Registers (MBCCSRn) Section 3.4.6.2, “Single Transmit Message Section 3.4.6.4, “Double Transmit Message MFR4300 Data Sheet, Rev. 3 Message Buffer Data Size Message Buffer Table 3-89. Reserved Buffers”, Section 3.4.6.3, Buffer” ...

Page 153

... Message Data and Slot Status Access read-only Message Header Access for Null Frame Transmission read/write Message Transmission and Slot Status Update read-only Message Buffer Validation read-only Message Buffer Search MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Table 3-90 region is active CMT SR Region used for ...

Page 154

... Excluded from message buffer search. CFG – Disabled and Locked - Message Buffer under configuration. Excluded from message buffer search. MSG SR Locked - Applications access to data, control, and status. Included in message buffer search. MFR4300 Data Sheet, Rev. 3 Table 3-91, which also SU CCSu SSS CCTx TX DSS ...

Page 155

... Status Update - Message buffer status update. Update of status flags, the slot status field, and the header index. CHI Error Flag Register (CHIERFR) Condition MBCCSRn.EDS = 0 Application triggers message buffer enable. MBCCSRn.EDS = 1 Application triggers message buffer disable. MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Description Message Buffer Configuration, is set. Description ...

Page 156

... Dynamic Slot or Segment Start. - Start of dynamic slot or symbol window or NIT. Slot or Segment Start - Start of static slot or dynamic slot or symbol window or NIT. 3-94, the module transitions have a higher priority than the application Description module vs. application MFR4300 Data Sheet, Rev. 3 Description Table 3-93. Each Description Table 3-94. ...

Page 157

... MBCCSRn.CMT = ‘1’. Freescale Semiconductor module internal Message Buffer Configuration, Control, Status Buffers”. Table 3-92. The state change is indicated through the MBCCSRn.EDS and Section 3.4.7, “Individual Message Buffer MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Description Search”, 157 ...

Page 158

... FlexRay module triggers the slot assigned transition SA for up to two transmit message buffers if at 158 CCMa message transmit (MBSSUTR). Description” Section 3.4.7, “Individual Message Buffer MFR4300 Data Sheet, Rev. 3 SSS SU CCTx CCSu message transmit slot s+1 slot s+2 SSS Idle CCTx ...

Page 159

... Freescale Semiconductor STS STS HLckCCNf null frame transmit Figure 3-116. HU STS CCSa null frame transmit Figure MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Figure 3-114. SSS CCNf null frame transmit slot s+1 slot s+2 SSS HLck slot s+1 slot s+2 ...

Page 160

... In any of these two cases, the status of the message buffer is not changed at all with the SU transition. The slot status field is not updated, the status and control flags are not changed, and the interrupt flag is not set. 160 ST HL CCNf null frame transmit (PIFR1). MFR4300 Data Sheet, Rev HLckCCNf HLck slot s+1 slot s+2 Freescale Semiconductor ...

Page 161

... If an region is active as indicated in Message Buffer Header Field: Data Field Offset Message Buffer Header Field: Frame Header Message Buffer Header Field: Slot Status Message Buffer Data Field: DATA[0-N] MBIDXRn.MBIDX MBCCSRn.DVAL/DUP MBCCSRn.MTD MBCCFRn.CHA/CHB/CCF* MBFIDRn.FID MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2 161 ...

Page 162

... HLckCCBs Access from Appl. Module – SR Idle - Message Buffer is idle. Included in message buffer search. CFG – Disabled - Message Buffer under configuration. Excluded from message buffer search. MFR4300 Data Sheet, Rev. 3 Region used for Table SU CCSu SSS CCRx HL HU HLckCCRx SSS Description ...

Page 163

... CHI Error Flag Register (CHIERFR) Condition MBCCSRn.EDS = 0 Application triggers message buffer enable. MBCCSRn.EDS = 1 Application triggers message buffer disable. MBCCSRn.LCKS = 0 Application triggers message buffer lock. MBCCSRn.LCKS = 1 Application triggers message buffer unlock. MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Description Message Buffer Configuration, is set. Description ...

Page 164

... Slot or Segment Start - Start of either Static Slot, Dynamic Slot, Symbol Window, or NIT. Status Updated - Slot Status field, message buffer status flags, header index updated. Interrupt flag set. Description module vs. application Section 3.4.7.1, “Individual Message Buffer MFR4300 Data Sheet, Rev. 3 Table 3-98. Each Freescale Semiconductor ...

Page 165

... Valid null frame received. - Message Buffer Data Field not updated. - Frame Header Field not updated. - Slot Status Field updated. - DUP DVAL not changed - MBIF:= 1 MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Concept”. The data and status of Table 3-100. Update description 165 ...

Page 166

... Note: An empty dynamic slot is indicated by the following frame and slot status bit values: vSS!ValidFrame vSS!ContentError NOTE Figure 3-120. SLS message receive to receive shadow buffer Figure 3-120. Message Reception Timing (MBSSUTR). MFR4300 Data Sheet, Rev. 3 Update description = 0 and vSS!SyntaxError = 0 and = 0 and vSS!BViolation = 0. SSS SU CCSu ...

Page 167

... The other side is called the transmit side and is used by the Freescale Semiconductor Section 3.4.3.1, “Individual Message Buffers”. 3-100), the FlexRay module writes the slot status into the slot status Message Buffer Index Registers MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Buffers”. Message Buffer Index Registers (MBIDXRn). Message Buffer Index ...

Page 168

... MBIDXR[2n+1].MBIDX ITX MBCCSR[2n+1].CMT Message Buffer Data Field: DATA[0-N] SS Message Buffer Header Field: Slot Status MBCCSR[2n+1].MBT/MTD MBCCFR[2n+1].MTM/CHA/CHB/CCF* MBFIDR[2n+1].FID MFR4300 Data Sheet, Rev. 3 FlexRay Bus message data Transmit Side (MBIDXRn). Figure 3-122. The given regions Transmit Side Freescale Semiconductor ...

Page 169

... Message Buffer Search read-only Internal Message Transfer, Message Transmission write-only Slot Status Update Table 3-103. The states for the transmit side of a double Figure 3-124. A description of the states is given in MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Description Table 3-103. The 169 ...

Page 170

... Disabled and Locked - Message Buffer under configuration. SS Commit Side can not be used for internal message transfer. MSG Locked - Applications access to data, control, and status. SS Commit Side can not be used for internal message transfer. MFR4300 Data Sheet, Rev. 3 Table 3-102. Description Freescale Semiconductor ...

Page 171

... Message Buffer Data transferred from commit side to transmit side. – TX Message Transmission - Message buffer data transmit. Payload data from buffer transmitted MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) SU CCSu SSS CCTx ...

Page 172

... MBCCSR[2n+1].EDS = 0 Application triggers message buffer enable. MBCCSR[2n+1].EDS = 1 Application triggers message buffer disable. MBCCSR[2n].LCKS = 0 Application triggers message buffer lock. MBCCSR[2n].LCKS = 1 Application triggers message buffer unlock. MFR4300 Data Sheet, Rev. 3 Description Message Buffer Configuration, CHI Error Flag Register Description Table 3-105 ...

Page 173

... Dynamic Slot or Segment Start. - Start of dynamic slot or symbol window or NIT. Slot or Segment Start - Start of static slot or dynamic slot or symbol window or NIT. 3-106, the module transitions have a higher priority than the application Description module vs. application module internal MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Description 173 ...

Page 174

... MBCCSR[2n+1].CMT = 0 or the message data were transmitted at least once, i.e. MBCCSR[2n+1].DVAL = 1 174 Section 3.4.6.4.5, “Internal Message Transfer Buffers”. Message Buffer Configuration, Control, Status Registers Streaming Commit Mode (MBCCSRn). MFR4300 Data Sheet, Rev. 3 Message Buffer Configuration, Message Buffer Index and Immediate Freescale Semiconductor ...

Page 175

... Freescale Semiconductor CCITx Idle HLck CCITx (MBCCSRn CCITx Idle HLck CCITx Idle MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Figure 3-125. In this example, HU Idle no internal message transfer, until message transmitted Idle slot s+1 slot s+2 Figure 3-126. In this example Idle ...

Page 176

... If all message buffers assigned or subscribed to the next slot are assigned to both channels, only one sorted list of matching message buffers is created. 176 Section 3.4.6.2.7, “Message Buffer Section 3.4.7.1, “Individual Message MFR4300 Data Sheet, Rev. 3 CHI Freescale Semiconductor ...

Page 177

... Message Buffer Frame ID Registers (MBFIDRn) MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Table 3-107. From the group with the Description equals s. (MBCCFRn). This filter determines ...

Page 178

... MBCCFRn.CCFE == 0 defines the channels on which the message buffer will receive or MBCCFR0.CHA = 1, MBCCFR0.CHB = 0 MBCCFR1.CHA = 1, MBCCFR1.CHB = 1 Specific Configuration Data POC:config state. Figure MFR4300 Data Sheet, Rev. 3 Eqn. 3-8 Eqn. 3-9 Message Buffer Cycle Figure 3-127. single channel assignment dual channel assignment Specific Configuration can not be 3-128 ...

Page 179

... Size Register (RFDSR) Freescale Semiconductor RC2 double TX (commit side) double TX (transmit side) RC1 Section 3.4.3.3, “Receive FIFO”. Receive FIFO Start Index Register (RFSIR) MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Figure 3-128. The RC3 RC1 single TX RC3 The area in Receive FIFO Depth ...

Page 180

... NOTE Figure 3-129 Global Interrupt Flag and Enable Register (RFBRIR), respectively. This index points to the Section 3.4.3.3, “Receive FIFO”. MFR4300 Data Sheet, Rev. 3 POC:config. Receive FIFO Depth and Size is activated. Global Interrupt Flag and Enable Receive FIFO A Read Index Register ...

Page 181

... Only frames that have passed all filters will be appended to the FIFO. The FIFO filter path is depicted in Freescale Semiconductor (RFBRIR), respectively.When the RDIDX (RFSIR). Figure 3-129. MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Receive FIFO A Read Index 181 ...

Page 182

... Frame ID Range rejection filter Frame ID Range acceptance filter no frame received in dynamic segment no message ID (vRF!Header!PPIndicator=’1’) Message ID acceptance filter no set fifo overflow interrupt flag ignore frame and the is fulfilled. MFR4300 Data Sheet, Rev yes no else passed else passed else passed yes yes ...

Page 183

... The RX FIFO Frame ID range filters apply to Equation 3-12 (RFRFCTR). The RX FIFO Frame ID range filters apply to and the (RFMIAFMR). This filter applies only to valid frames received in the MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) and controlled by the Equation 3-11 is fulfilled. Eqn. 3-11 for at least one of the enabled rejection Eqn ...

Page 184

... RXD_BG1 TXD_BG1 channel 0 TXEN1# RXD_BG2 TXD_BG2 channel 1 TXEN2# Figure 3-130. Dual Channel Device Mode Figure 3-131) or the physical bus channel B (shown in MFR4300 Data Sheet, Rev. 3 FlexRay Channel FlexRay Bus Driver Channel A FlexRay Channel FlexRay Bus Driver Channel B Figure Freescale Semiconductor Eqn. 3- 3-132) ...

Page 185

... TXEN1# RXD_BG2 TXD_BG2 channel B TXEN2# RXD_BG1 TXD_BG1 channel A TXEN1# Init Value for Frame CRC is cCrcInit[A] RXD_BG2 TXD_BG2 channel B TXEN2# MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) FlexRay Channel FlexRay Bus Driver Channel A FlexRay Channel FlexRay Bus Driver Channel A cCrcInit[ 185 ...

Page 186

... Protocol Operation Control Register Figure 3-133 NIT static segment cycle 2n+1 static segment NIT static segment cycle 2n+1 cycle 2n+2 NOTE MFR4300 Data Sheet, Rev. 3 (POCR). The PE applies the Figure 3-133 and Figure for timing details. EOC_AP application NIT Figure 3-134 ERC_AP application NIT ...

Page 187

... Sync Frame ID ChB 15 Figure 3-135. Sync Table Memory Layout Figure 3-135. Each table occupies 120 16-bit entries. state, the application must program the offsets for the tables into the (SFTOR). MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) vsSyncIdListA and vsSyncIdListB SFTOR + 180 ...

Page 188

... After reading all the data from the locked tables, the application must unlock the table by writing to the even table lock trigger SFTCCSR.ELKT again. The even table lock status bit SFTCCSR.ELKS is reset immediately. 188 Table 3-108. Description (PIFR1). If the interrupt enable flag (SFCNTR). The value in the SFTCCSR.CYCNUM field provides the MFR4300 Data Sheet, Rev. 3 (SFTCCSR). A Freescale Semiconductor ...

Page 189

... NIT cycle 2n (SFTCCSR). If the affected table is not and MTS B Configuration Register are fulfilled. MTSACFR.MTE = 1 MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) are updated. This is done Sync Frame Counter Register even table write odd table write static segment NIT cycle 2n+1 MTS A (MTSBCFR) ...

Page 190

... Sync Frame Filtering Each received synchronization frame must pass the Sync Frame Acceptance Filter and the Sync Frame Rejection Filter before it is considered for clock synchronization. If the synchronization frame filtering is 190 are fulfilled. MTSBCFR.MTE = 1 MFR4300 Data Sheet, Rev. 3 Eqn. 3-17 Equation 3-15, Eqn. 3-18 Eqn. 3-19 ...

Page 191

... MCR.SFFE == 0 > SFIDRFR.SYNFRID[9:0] NOTE Table 3-11 can be assigned to one of the four strobe ports using the (STBSCR). To assign multiple strobe signals, the application must write MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) is cleared, all and the mask is configured in the or Equation 3-21evaluates to evaluates to true. ...

Page 192

... The application must restart the timers when the protocol has reached the 192 -2 Table 3-11 with a positive clock offset. An example waveform is given +4 Both timers can be configured to be repetitive. In the . POC:normal active POC:normal active or POC:normal passive MFR4300 Data Sheet, Rev. 3 Figure 3-137. or POC:normal passive state. If state. Freescale Semiconductor ...

Page 193

... Protocol Interrupt Flag Register 0 (PIFR0) Protocol Interrupt Enable Register 0 (PIER0) and Timer 2 Configuration Register 1 3-109. The PE provides the slot status vector within the first macrotick Figure 3-139. MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) is set at the macrotick start event, Eqn. 3-24 Eqn. 3-25 is asserted, is used. ...

Page 194

... Figure 3-139. Slot Status Vector Update NOTE Table 3-109. Slot Status Content Status Content - content error occurred while receiving vSS!ValidFrame = 1 vSS!ValidFrame = 0 - Null Frame Indicator (0 for null frame) - Startup Frame Indicator - Sync Frame Indicator MFR4300 Data Sheet, Rev. 3 NIT Freescale Semiconductor ...

Page 195

... Network Idle Time NIT (SSR0–SSR7), can be used to observe the status of Slot Status Counter Condition Register MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) vSS!TxConflict is set to ‘1’. The ...

Page 196

... SSCRn_INT not updated dynamic segment symbol window communication cycle NOTE MFR4300 Data Sheet, Rev. 3 Figure 3-140. incr. SSCRn_INT on error SSCRn:= SSCRn_INT NIT Freescale Semiconductor ...

Page 197

... Freescale Semiconductor for the static/dynamic slot. The update conditions for the slot status Description”. if the corresponding Receive FIFO is not empty. and Protocol Interrupt Flag Register 1 MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Section 3.4.6, Global Interrupt Protocol (PIFR1). Each interrupt source ...

Page 198

... GIFER.CHIE is set. 3.4.19.2.5 Module Interrupt The combined module interrupt request MIRQ is generated if at least one of the combined interrupt sources generates an interrupt request and the interrupt enable bit GIFER.MIE is set. 198 MFR4300 Data Sheet, Rev. 3 CHI Error Freescale Semiconductor ...

Page 199

... GIFER.RBIF n OR & GIFER.RBIE Receive GIFER.TBIF n OR & GIFER.TBIE Transmit GIFER.CHIF OR GIFER.PRIF OR GIFER.PRIE MFR4300 Data Sheet, Rev. 3 FlexRay Module (FLEXRAYV2) Interrupt Signals MBXIRQ[n-1:0] CHIXIRQ[15:0] PRTXIRQ[31:16] PRTXIRQ[15:0] RBIRQ & TBIRQ & CHIIRQ PRTIRQ & FNEAIRQ & FNEBIRQ & WUPIRQ & GIFER.MIF ...

Page 200

... GIFER.FNEBIF GIFER.WUPIF Figure 3-143. Scheme of combined interrupt flags 200 OR Figure 3-142. INT_CC# generation scheme Message Buffers n OR & Transmit n OR & Receive OR OR MFR4300 Data Sheet, Rev. 3 INT_CC# Combined Interrupt Flags CIFR.TBIF CIFR.RBIF CIFR.CHIF CIFR.PRIF CIFR.MIF OR CIFR.FNEAIF CIFR.FNEBIF CIFR.WUPIF Freescale Semiconductor ...